CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
ANALOG CHARACTERISTICS
Maximum Conversion Rate
Minimum Conversion Rate
Input Bandwidth Full Scale
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 3 to 5.5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
SYMBOL
TEST CONDITIONS
AV
DD
= 4.75 to 5.25V, T
A
= 20 to 75
o
C, V
IN
=
0.5 to 2.5V,
f
IN
= 1kHz Triangular Wave
Envelope
R
IN
= 33Ω
End Point
-1dB
-3dB
NOTES
MIN
TYP
MAX
UNITS
f
C
Max
f
C
Min
BW
50
-
-
-
-
-
65
-
60
100
±0.3
+0.7
-50
40
3
1.5
0
20
20
-
0.5
-
-
±0.5
±1.5
-30
60
-
-
-
40
40
MSPS
MSPS
MHz
MHz
LSB
LSB
mV
mV
%
Degrees
ns
mV
mV
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Voltage
E
D
E
L
E
OT
E
OB
DG
DP
t
SD
E
OC
Potential Difference to V
RT
Potential Difference to V
RB
NTSC 40 IRE Mod Ramp
f
C
= 14.3 MSPS
Note 2
-70
20
-
-
-
Differential Gain Error
Differential Phase Error
Sampling Delay
Clamp Offset Voltage
V
IN
= DC, C
IN
= 10µF
t
PCW
= 2.75µs,
f
C
= 14.3 MSPS,
f
CLP
= 15.75kHz
f
IN
= 100kHz
f
IN
= 500kHz
f
IN
= 1MHz
f
IN
= 3MHz
f
IN
= 10MHz
f
IN
= 25MHz
V
REF
= 0.5V
V
REF
= 2.5V
0
0
Signal-To-Noise Ratio
SNR
-
-
-
-
-
-
-
-
-
-
-
-
45
44
44
43
38
32
51
46
49
46
45
45
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Spurious Free Dynamic
SFDR
f
IN
= 100kHz
f
IN
= 500kHz
f
IN
= 1MHz
f
IN
= 3MHz
f
IN
= 10MHz
f
IN
= 25MHz
3
HI2302
Electrical Specifications
PARAMETER
DC CHARACTERISTICS
Supply Current
Analog
Digital
Reference Current
Reference Resistance
(V
RT
- V
RB
)
Self-Bias Voltage
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 3 to 5.5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
(Continued)
SYMBOL
TEST CONDITIONS
NOTES
MIN
TYP
MAX
UNITS
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 5V or 3.3V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
I
AD
+ I
DD
I
AD
I
DD
I
REF
R
REF
V
RB
V
RT -
V
RB
C
AI1
C
AI2
C
DIN
Shorts V
RTS
and A
VDD
Shorts V
RBS
and A
VSS
V
IN
, V
IN
= 1.5V + 0.07V
RMS
V
RTS
, V
RT
, V
RB
, V
RBS
, V
REF
TEST, CLK, CLP, CLE, OE
CCP
D0 to D7, TEST
AV
DD
= 4.75 to 5.25V,
DV
DD
= 3 to 5.5V, T
A
= -20
o
C to 75
o
C
V
I
= 0V to AV
DD
,
T
A
= 20
o
C to 75
o
C
CLK
TEST, CLP, CLE
OE
NTSC Ramp,
Wave Input,
CLE = 0V
DV
DD
= 5V
DV
DD
= 3.3V
-
-
-
4.1
260
0.52
1.80
-
-
-
-
-
2.2
-
-240
-240
-40
-
4
-
2.4
-40
-40
25
23
2
5.4
370
0.56
1.92
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
36
33
3
7.7
480
0.60
2.04
-
11
11
11
11
-
0.8
240
40
240
-2
-
-1.2
-
40
40
mA
mA
mA
mA
Ω
V
V
pF
pF
pF
pF
pF
V
V
µA
µA
µA
mA
mA
mA
mA
µA
µA
Input Capacitance
Output Capacitance
C
AO
C
DO
V
IH
V
IL
I
IH
I
IL
Digital Input Voltage
Digital Input Current
Digital Output Current
I
OH
I
OL
I
OH
I
OL
I
OZH
I
OZL
OE = 0V, DV
DD
= 5V
T
A
= 20
o
C to 75
o
C
OE = 0V
DV
DD
= 3.3V
T
A
= -20
o
C to 75
o
C
OE = 3V
DV
DD
= 3 to 5.5V
T
A
= -20
o
C to 75
o
C
CL = 15pF
OE = 0V
V
OH
= DV
DD
- 0.8V
V
OL
= 0.4V
V
OH
= DV
DD
- 0.8V
V
OL
= 0.4V
V
OH
= DV
DD
V
OL
= 0V
TIMING
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 5V or 3.3V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
t
PZH
t
PHL
t
PLH
t
PHL
DV
DD
= 5V
DV
DD
= 3.3V
R
L
= 1kΩ
C
L
= 15pF
OE = 3V➝0V
DV
DD
= 5V
DV
DD
= 3.3V
R
L
= 1kΩ, C
L
= 15pF
OE = 3V➝0V
DV
DD
= 5V
DV
DD
= 3.3V
Note 4
5.5
9.5
8.5
4.3
11.8
7.6
2.5
4.5
6.0
3.0
7.0
5.0
3.5
2.5
1.75
5.5
5.5
2.75
7.5
8.0
3.75
9.0
8.0
16.3
12.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Output Data Delay
Three-State Output Enable
Time
t
PZH
t
PZL
t
PZH
t
PZL
Three-State Output Enable
Time
Clamp Pulse Width
NOTES:
t
PHZ
, t
PLZ
t
PZH
, t
PZL
t
CPW
f
C
= 14.3MHz, C
IN
= 10µF for NTSC Wave
2. The offset voltage E
OB
is a potential difference between V
RB
and a point of position where the voltage drops equivalent to
1
/
2
LSB of the voltage
when the output data changes from “00000000” to “00000001”. E
OT
is a potential difference between V
RT
and a potential point where the
voltage rises equivalent to
1
/
2
LSB of the voltage when the output data changes from “11111111” to “11111110”.
3. The voltage of up to (AV
DD
+ 0.5V) can be input when DV
DD
= 3.3V. But the output pin voltage is less than the DV
DD
voltage. When the digital
output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DV
DD
+ 0.5V) voltage to the
digital output.
4. The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing systems
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