Maximum Storage Temperature Range . . . . . . . . .-65×°C to 150°C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300°C
*Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than V
DD
or less than V
SS
may cause
destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be
applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211AM be turned on first.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CHARACTERISTICS
V
DD
= 5V
±10%,
T
A
= 25°C, V
SS
= 0V Unless Otherwise Specified
Operating Supply Voltage Range (V
DD
- V
SS
), V
SUPPLY
Operating Current, I
DD
Oscillator Input Current, I
OSCI
Segment Rise/Fall Time, t
r
, t
f
Backplane Rise/Fall Time, t
r
, t
f
Oscillator Frequency, f
OSC
Backplane Frequency, f
BP
INPUT CHARACTERISTICS
Logical “1” Input Voltage, V
IH
Logical “0” Input Voltage, V
IL
Input Leakage Current, I
ILK
Input Capacitance, C
lN
BP/Brightness Input Leakage, I
BPLK
BP/Brightness Input Capacitance, C
BPI
AC CHARACTERISTICS
Chip Select Active Pulse Width, t
WL
Data Setup Time, t
DS
Data Hold Time, t
DH
Inter-Chip Select Time, t
ICS
Other Chip Select Either Held Active, or
Both Driven Together
200
100
10
2
-
-
0
-
-
-
-
-
ns
ns
ns
µs
Pins 27-34
Pins 27-34
Measured at Pin 5 with Pin 36 at V
SS
All Devices
4
-
-
-
-
-
-
-
±0.01
5
±0.01
200
-
1
±1
-
±1
-
V
V
µA
pF
µA
pF
Test circuit, Display blank
Pin 36
C
L
= 200pF
C
L
= 5000pF
Pin 36 Floating
Pin 36 Floating
3
-
-
-
-
-
-
5
10
±2
0.5
1.5
19
150
6
50
±10
-
-
-
-
V
µA
µA
µs
µs
kHz
Hz
3
FN3158.7
April 17, 2006
ICM7211AM
Input Definitions
In this table, V
DD
and V
SS
are considered to be normal operating input logic levels. Actual input low and high levels are specified
under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT
B0
B1
B2
B3
OSC
DIP TERMINAL
27
28
29
30
36
CONDITIONS
V
DD
= Logical One
V
SS
= Logical Zero
V
DD
= Logical One
V
SS
= Logical Zero
V
DD
= Logical One
V
SS
= Logical Zero
V
DD
= Logical One
V
SS
= Logical Zero
Floating or with External
Capacitor to V
DD
V
SS
Ones (Least Significant)
Twos
Data Input Bits
Fours
Eights (Most Significant)
Oscillator Input
Disables BP output devices, allowing segments to be synchronized to an
external signal input at the BP terminal (Pin 5).
FUNCTION
Interface Input Configuration
INPUT
DA1
DA2
DESCRIPTION
Digit Address
Bit 1 (LSB)
Digit Address
Bit 2 (MSB)
Chip Select 1
Chip Select 2
DIP TERMINAL
31
32
CONDITIONS
V
DD
= Logical One
V
SS
= Logical Zero
V
DD
= Logical One
V
SS
= Logical Zero
V
DD
= Inactive
V
SS
= Active
V
DD
= Inactive
V
SS
= Active
FUNCTION
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
When both CS1 and CS2 are taken low, the data at the Data and Digit
Select code inputs are written into the input latches. On the rising edge
of either Chip Select, the data is decoded and written into the output
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