CY22388
CY22389
CY22391
Factory Programmable Quad PLL
Clock Generator with VCXO
Factory Programmable Quad PLL Clock Generator with VCXO
Features
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Benefits
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Fully integrated phase-locked loops (PLLs)
Small quad flat no-leads (QFN) package option
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40% smaller than 20-pin TSSOP
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22% smaller than 16-pin TSSOP
Selectable output frequency
Programmable output frequencies
Output frequency range:
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1 MHz to 166 MHz
Input frequency range:
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Crystal: 10 MHz to 30 MHz
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External reference: 1 MHz to 100 MHz
Analog voltage-control crystal oscillator (VCXO)
16-/20-pin TSSOP and 32-pin QFN packages
3.3-V operation with 2.5-V output buffer option
Meets most digital set top box, DVD recorder, and DTV
application requirements
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Integration eliminates the need for external loop filter
components
Meets critical timing requirements in complex system designs
Enables application compatibility
Complete VCXO solution with ±120 ppm (typical pull range)
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Functional Description
For a complete list of related documentation, click
here.
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Logic Block Diagram
FS0
FS1
FS2
Select
Logic
CLKA
PLL1
CLKB
CLKC
XIN
XOUT
VIN
VCXO
PLL2
Dividers
&
Multiplexers
PLL3
CLKD
CLKE
CLKF
(CY22389 &
CY22391 only)
(CY22389 &
CY22391 only)
(CY22389 &
CY22391 only)
PLL4
CLKG
CLKH
OE/PD#
(CY22389 &
CY22391 only)
Cypress Semiconductor Corporation
Document Number: 38-07734 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 15, 2017
CY22388
CY22389
CY22391
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
General Description ......................................................... 5
Factory-Programmable CY22388/89/91 ...................... 5
PLLs ................................................................................... 5
Frequency Select Pin Operation ..................................... 5
Analog VCXO .................................................................... 6
VCXO Profile ..................................................................... 6
Absolute Maximum Conditions ....................................... 7
Pullable Crystal Specifications ....................................... 7
Operating Conditions ....................................................... 7
DC Parameters .................................................................. 8
AC Parameters .................................................................. 9
Test and Measurement ..................................................... 9
Voltage and Timing Definitions ..................................... 10
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definitions ......................................... 11
Package Drawing and Dimensions ............................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC®Solutions ....................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 38-07734 Rev. *J
Page 2 of 17
CY22388
CY22389
CY22391
General Description
The CY22388 family of devices has an analog VCXO, four PLLs,
up to eight clock outputs and frequency selection capabilities.
The frequency selects do not modify any PLL frequency. Instead
they allow the user to choose among eight different output divider
selections depending on the clock and package configuration.
This is illustrated in the
Frequency Select Pin Operation
tables
and
on page 1.
There is one programmable OE/PD#. The OE/PD# pin can be
programmed as either an output enable pin or a power-down pin.
The OE function can be programmed to disable a selected set of
outputs when low, leaving the remaining outputs running.
Full-chip power-down disables all outputs and the PLLs and
most of the active circuitry when low.
CLKC and CLKE have related frequencies. Related frequencies
come from the same PLL but can have different divider values.
To minimize parts per million (PPM) error on the clock outputs,
you must choose a crystal reference frequency that is a common
multiple of the desired PLL frequencies. While this is the ideal
situation, this is not always the case and the PLLs have
high-resolution counters internally to help minimize frequency
deviation from the desired frequency.
PLL VCO frequencies are generated by the following equation:
F
VCO
= F
REF
* (P / Q)
where F
REF
is the reference input frequency, P is the PLL
feedback divider, and Q is the reference input divider.
A PLL is a feedback system where the VCO frequency divided
by P and reference frequency divided by Q are constantly being
compared and the VCO frequency is adjusted to achieve a
locked state.
Figure 4
is a simplified drawing of a PLL.
Figure 4. PLL system
F
R E F
Factory-Programmable CY22388/89/91
Factory programming is available for high- or low-volume
manufacturing by Cypress. All requests must be submitted to the
local Cypress field application engineer (FAE) or sales
representative. After the request is processed, you receive a new
part number, samples, and datasheet with the programmed
values. This part number is used for additional sample requests
and production orders.
/Q
V C O
a nd
F
V C O
O th e r
c o m p o n e n ts
/P
PLLs
The advantage of having four PLLs is that a single device can
generate up to four independent frequencies from a single
crystal. Generally a design may require up to four oscillators to
accomplish what could be done with a single CY22388.
Each PLL is independent and can be configured to generate a
voltage-controlled oscillator (VCO) frequency between
62.5 MHz and 250 MHz. Each PLL can then, in turn, be divided
down with post dividers to generate the clock output frequency
of the user’s choice. The output divider allows each clock output
to be divided by 1, 2, 3, 4, 5, 6, 8, 9, 10, 12 or 15. The PLL
maximum is reduced to 166 MHz in ‘divide by 1’ mode due to
output buffer limitations.
Outputs that allow frequency switching perform a glitch-free
transition. A glitch is defined as a high- or low-time shorter than
half the smaller of the two periods being switched between.
Extended low time (even many cycles in duration) is acceptable.
Selected clock outputs are capable of being powered off a
separate 2.5-V supply. This allows for driving lower voltage swing
inputs. The CY22388/89/91 device still requires 3.3 V to power
the oscillator and all other internal PLL circuitry. For the 2.5-V
output option, refer to the
CY22388 application note.
Selected
clocks and pinout diagrams are explained in this application
note.
Clock D can obtain its output from either the reference source or
PLL1/N1 with N1 being defined as the output divider for PLL1.
Clock H is defined as a copy of clock D. Clock D is only available
from PLL1/N1 on the 16-pin package.
For CY22388, CLKB and CLKC have related frequencies. For
CY22389 and CY22391, CLKD and CLKF have related
frequencies, CLKA and CLKB have related frequencies, and
Frequency Select Pin Operation
Table 1. CY22388 16-pin TSSOP
Output Signal
CLK A
CLK B
CLK C & CLK D
CLK E
Frequency Selection Lines
FS2, FS1, FS0
FS1, FS0
S0
FIXED
Table 2. CY22389 20-pin TSSOP
Output Signal
CLK A
CLK B & CLK C
CLK D, CLK E, & CLK F
CLK G
CLK H
Table 3. CY22391 32-pin QFN
Output Signal
CLK A
CLK B & CLK C
CLK D, CLK E, & CLK F
CLK G
CLK H
Frequency Selection Lines
FS2, FS1, FS0
FS1, FS0
FS0
FIXED
COPY OF CLK D
Frequency Selection Lines
FS2, FS1, FS0
FS1, FS0
FS0
FIXED
COPY OF CLK D
Document Number: 38-07734 Rev. *J
Page 5 of 17
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