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74AHC374PW112

Description
Flip Flops OCTAL D FLIP FLOP
Categorysemiconductor    logic   
File Size595KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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74AHC374PW112 Overview

Flip Flops OCTAL D FLIP FLOP

74AHC374PW112 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerNXP
Product CategoryFlip Flops
RoHSDetails
Number of Circuits1
Logic FamilyAHC
Logic TypeD-Type Edge Triggered Flip-Flop
PolarityNon-Inverting
Input TypeSingle-Ended
Output TypeSingle-Ended
Propagation Delay Time4.4 ns at 5 V
High Level Output Current- 8 mA
Low Level Output Current8 mA
Supply Voltage - Min2 V
Supply Voltage - Max5.5 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 125 C
Mounting StyleSMD/SMT
Package / CaseSOT-360
PackagingTube
FunctionD-Type Bus Interface
Height0.95 mm
Length6.6 mm
Width4.5 mm
Number of Channels8
Number of Input Lines8
Number of Output Lines8
NumOfPackaging1
Operating Supply Voltage5 V
Factory Pack Quantity1875
Unit Weight0.000212 oz
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 03 — 12 June 2008
Product data sheet
1. General description
The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input
(CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and
hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Common 3-state output enable input
Input levels:
N
For 74AHC374: CMOS level
N
For 74AHCT374: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C

74AHC374PW112 Related Products

74AHC374PW112 74AHC374D112 74AHCT374D118 74AHCT374PW112
Description Flip Flops OCTAL D FLIP FLOP Flip Flops OCTAL D 3-STATE Flip Flops OCTAL D 3-STATE Flip Flops OCTAL D 3-STATE
Product Attribute Attribute Value Attribute Value Attribute Value Attribute Value
Manufacturer NXP NXP NXP NXP
Product Category Flip Flops Flip Flops Flip Flops Flip Flops
RoHS Details Details Details Details
Number of Circuits 1 1 1 1
Logic Family AHC AHC AHCT AHCT
Logic Type D-Type Edge Triggered Flip-Flop D-Type Edge Triggered Flip-Flop D-Type Edge Triggered Flip-Flop D-Type Edge Triggered Flip-Flop
Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting
Input Type Single-Ended Single-Ended Single-Ended Single-Ended
Output Type Single-Ended Single-Ended Single-Ended Single-Ended
Propagation Delay Time 4.4 ns at 5 V 4.4 ns at 5 V 4.3 ns 4.3 ns
High Level Output Current - 8 mA - 8 mA - 8 mA - 8 mA
Low Level Output Current 8 mA 8 mA 8 mA 8 mA
Supply Voltage - Min 2 V 2 V 4.5 V 4.5 V
Supply Voltage - Max 5.5 V 5.5 V 5.5 V 5.5 V
Minimum Operating Temperature - 40 C - 40 C - 40 C - 40 C
Maximum Operating Temperature + 125 C + 125 C + 125 C + 125 C
Mounting Style SMD/SMT SMD/SMT SMD/SMT SMD/SMT
Package / Case SOT-360 SOT-163 SOT-163 SOT-360
Function D-Type Bus Interface D-Type Bus Interface D-Type Bus Interface D-Type Bus Interface
Height 0.95 mm 2.45 mm 2.45 mm 0.95 mm
Length 6.6 mm 13 mm 13 mm 6.6 mm
Width 4.5 mm 7.6 mm 7.6 mm 4.5 mm
Number of Channels 8 8 8 8
Number of Input Lines 8 8 8 8
Number of Output Lines 8 8 8 8
NumOfPackaging 1 1 3 1
Operating Supply Voltage 5 V 5 V 5 V 5 V
Factory Pack Quantity 1875 1520 2000 1875
Packaging Tube Tube Reel Tube
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