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ispLSI-2128VE-250LT100

Description
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Categorysemiconductor    Programmable logic devices   
File Size198KB,21 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
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ispLSI-2128VE-250LT100 Overview

CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD

ispLSI-2128VE-250LT100 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerLattice
Product CategoryCPLD - Complex Programmable Logic Devices
Shipping RestrictionsThis product may require additional documentation to export from the United States.
RoHSN
ProductispLSI 2128VE
Number of Macrocells128
Number of Logic Array Blocks - LABs32
Maximum Operating Frequency250 MHz
Propagation Delay - Max4 ns
Number of I/Os28 I/O
Operating Supply Voltage3.3 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseTQFP-176
PackagingTray
Height1.4 mm
Length14 mm
Memory TypeEEPROM
Width14 mm
Number of Gates6000
Moisture SensitiveYes
Operating Supply Current195 mA
Factory Pack Quantity90
Supply Voltage - Max3.6 V
Supply Voltage - Min3 V
Lead-
Free
Package
Options
Available!
ispLSI 2128VE
3.3V In-System Programmable
SuperFAST™ High Density PLD
Functional Block Diagram*
Output Routing Pool (ORP)
D7
Output Routing Pool (ORP)
®
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2128V Devices
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
f
max
= 250MHz Maximum Operating Frequency
t
pd
= 4.0ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• LEAD-FREE PACKAGE OPTIONS
Output Routing Pool (ORP)
D3
D2
D1
D0
C7
Output Routing Pool (ORP)
0139A/2128VE
D6
D5
D4
A0
A1
C6
A2
D
Q
C5
A3
D
Q
C4
Output Routing Pool (ORP)
A4
D
Q
GLB
C3
A5
D
Q
C2
A6
C1
A7
B0
B1
Global Routing Pool (GRP)
B2
B3
B4
B5
B6
B7
C0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
*128 I/O Version Shown
Description
The ispLSI 2128VE is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2128VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2128VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2004
2128ve_12
1
CLK 0
CLK 1
CLK 2
Output Routing Pool (ORP)
Logic
Array

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Description CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Manufacturer Lattice Lattice Lattice Lattice Lattice Lattice Lattice
Product Category CPLD - Complex Programmable Logic Devices CPLD - Complex Programmable Logic Devices CPLD - Complex Programmable Logic Devices CPLD - Complex Programmable Logic Devices CPLD - Complex Programmable Logic Devices CPLD - Complex Programmable Logic Devices CPLD - Complex Programmable Logic Devices
RoHS N No No No No No N
Product ispLSI 2128VE ispLSI 2128VE ispLSI 2128VE ispLSI 2128VE ispLSI 2128VE ispLSI 2128VE ispLSI 2128VE
Number of Macrocells 128 128 128 128 128 128 128
Number of Logic Array Blocks - LABs 32 32 32 32 32 32 32
Maximum Operating Frequency 250 MHz 135 MHz 135 MHz 100 MHz 250 MHz 135 MHz 100 MHz
Propagation Delay - Max 4 ns 4 ns 4 ns 4 ns 4 ns 4 ns 4 ns
Number of I/Os 28 I/O 28 I/O 28 I/O 28 I/O 28 I/O 28 I/O 28 I/O
Operating Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Minimum Operating Temperature 0 C 0 C 0 C 0 C 0 C 0 C 0 C
Maximum Operating Temperature + 70 C + 70 C + 70 C + 70 C + 70 C + 70 C + 70 C
Mounting Style SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
Package / Case TQFP-176 TQFP-100 TQFP-100 CABGA-100-28 CABGA-100-28 TQFP-100 TQFP-176
Packaging Tray Tray Tray Tray Tray Tray Tray
Height 1.4 mm 1.4 mm 1.2 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm
Length 14 mm 24 mm 17 mm 24 mm 24 mm 14 mm 14 mm
Memory Type EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM
Width 14 mm 24 mm 17 mm 24 mm 24 mm 14 mm 14 mm
Number of Gates 6000 6000 6000 6000 6000 6000 6000
Moisture Sensitive Yes Yes Yes Yes Yes Yes Yes
Operating Supply Current 195 mA 195 mA 195 mA 195 mA 195 mA 195 mA 195 mA
Factory Pack Quantity 90 40 90 40 40 90 90
Supply Voltage - Max 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Supply Voltage - Min 3 V 3 V 3 V 3 V 3 V 3 V 3 V
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