19-3361; Rev 3; 7/10
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
General Description
The MAX3205E/MAX3207E/MAX3208E low-capaci-
tance, ±15kV ESD-protection diode arrays with an inte-
grated transient voltage suppressor (TVS) clamp are
suitable for high-speed and general-signal ESD protec-
tion. Low input capacitance makes these devices ideal
for ESD protection of signals in HDTV, PC monitors
(DVI™, HDMI
®
), PC peripherals (FireWire
®
, USB 2.0),
server interconnect (PCI Express
®
, InfiniBand™),
datacom, and interchassis interconnect. Each channel
consists of a pair of diodes that steer ESD current puls-
es to V
CC
or GND.
The MAX3205E/MAX3207E/MAX3208E protect against
ESD pulses up to ±15kV Human Body Model, ±8kV
Contact Discharge, and ±15kV Air-Gap Discharge, as
specified in IEC 61000-4-2. An integrated TVS ensures
that the voltage rise seen on V
CC
during an ESD event
is clamped to a known voltage. These devices have a
2pF input capacitance per channel, and a channel-to-
channel capacitance variation of only 0.05pF, making
them ideal for use on high-speed, single-ended, or dif-
ferential signals.
The MAX3207E is a two-channel device suitable for
USB 1.1, USB 2.0 (480Mbps), and USB OTG applica-
tions. The MAX3208E is a four-channel device for
Ethernet and FireWire applications. The MAX3205E is a
six-channel device for cell phone connectors and
SVGA video connections.
The MAX3205E is available in 9-bump, tiny wafer-level
package (WLP) and 16-pin, 3mm x 3mm, thin QFN
packages. The MAX3207E is available in a small 6-pin
SOT23 package. The MAX3208E is available in 10-pin
µMAX
®
and 16-pin, 3mm x 3mm TQFN packages. All
devices are specified for the -40°C to +125°C automo-
tive operating temperature range.
Features
♦
Low Input Capacitance of 2pF Typical
♦
Low Channel-to-Channel Variation of 0.05pF
from I/O to I/O
♦
High-Speed Differential or Single-Ended ESD
Protection
±15kV–Human Body Model
±8kV–IEC 61000-4-2, Contact Discharge
±15kV–IEC 61000-4-2, Air-Gap Discharge
♦
Integrated Transient Voltage Suppressor (TVS)
♦
Optimized Pinout for Minimized Stub Inductance
on Controlled-Impedance Differential-
Transmission Line Routing
♦
-40°C to +125°C Automotive Operating
Temperature Range
♦
WLP Packaging Available
MAX3205E/MAX3207E/MAX3208E
Ordering Information
PART
MAX3205EAWL+T
MAX3205EATE+
MAX3207EAUT+T
MAX3208EAUB+
MAX3208EATE+
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
9 WLP
16 TQFN-EP*
6 SOT23
10 μMAX
16 TQFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP
= Exposed pad.
Selector Guide
PART
MAX3205EAWL+T
MAX3205EATE+
MAX3207EAUT+T
MAX3208EAUB+
MAX3208EATE+
ESD-PROTECTED
I/O PORTS
6
6
2
4
4
TOP MARK
AIN
ACO
ABVG
—
ACN
Applications
DVI Input/Output Protection
Set-Top Boxes
PDAs/Cell Phones
Graphics Controller Cards
Displays/Projectors
High-Speed, Full-Speed and Low-Speed USB
Port Protection
FireWire IEEE 1394 Ports
Consumer Equipment
High-Speed Differential Signal Protection
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
FireWire is a registered trademark of Apple Inc.
PCI Express is a registered service mark of PCI-SIG Corporation.
DVI is a trademark of Digital Display Working Group.
HDMI is a registered trademark and registered service mark of
HDMI Licensing, LCC.
InfiniBand is a trademark and service mark of InfiniBand Trade
Association.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
MAX3205E/MAX3207E/MAX3208E
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +6.0V
I/O_ to GND ................................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
6-Pin SOT23 (derate 8.7mW/°C above +70°C)............696mW
9-Bump WLP (derate 14.1mW/°C above +70°C).............0mW
10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW
16-Pin TQFN (derate 20.8mW/°C above +70°C) .......1667mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (excluding WLP; soldering, 10s) .......+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 1)
PARAMETER
Supply Voltage
Supply Current
Diode Forward Voltage
SYMBOL
V
CC
I
CC
V
F
I
F
= 10mA
T
A
= +25°C, ±15kV Human
Body Model, I
F
= 10A
Channel Clamp Voltage
(Note 2)
Positive transients
Negative transients
0.65
CONDITIONS
MIN
0.9
1
TYP
MAX
5.5
100
0.95
V
CC
+ 25
-25
V
CC
+ 60
-60
V
CC
+ 100
-100
-0.1
MAX3205EAWL+T
MAX3207EAUT+T
Channel I/O Capacitance
V
CC
= +3.3V, bias of V
CC
/ 2
MAX3205EATE+
MAX3208EATE+
MAX3208EAUB+
Channel I/O to I/O
Variation in Capacitance
TRANSIENT SUPPRESSOR
V
CC
Capacitance to GND
ESD Trigger Voltage
dV/dt
1V/ns (Note 3)
10
9
pF
V
C
IN
V
CC
= +3.3V, bias of V
CC
/ 2, C
I/O_
to GND
2.5
2.7
2.6
±0.05
+0.1
3
3.2
3.1
pF
pF
μA
V
UNITS
V
nA
V
V
C
T
A
= +25°C, ±8kV Contact Positive transients
Discharge (IEC 61000-4-2),
Negative transients
I
F
= 24A
T
A
= +25°C, ±15kV Air-Gap Positive transients
Discharge (IEC 61000-4-2),
Negative transients
I
F
= 45A
Channel Leakage Current
Note 1:
Parameters are 100% production tested at +25°C. Limits over temperature are guaranteed by design only.
Note 2:
Idealized clamp voltages. See the
Applications Information
section for more information.
Note 3:
Guaranteed by design, not production tested.
2
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Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Typical Operating Characteristics
(V
CC
= +5V, T
A
= +25°C, unless otherwise noted.)
CLAMP VOLTAGE
vs. DC CURRENT
MAX3205E toc01
MAX3205E/MAX3207E/MAX3208E
LEAKAGE CURRENT
vs. TEMPERATURE
MAX3205E toc02
INPUT CAPACITANCE
vs. INPUT VOLTAGE
MAX3205E toc03
1.5
1.3
CLAMP VOLTAGE (V)
1.1
0.9
0.7
GND TO I/O_
0.5
0.3
10
30
50
70
90
110
130
I/O_ TO V
CC
10,000
4
INPUT CAPACITANCE (pF)
LEAKAGE CURRENT (pA)
1000
3
100
2
10
1
1
150
-40
0
40
80
120
DC CURRENT (mA)
TEMPERATURE (°C)
0
0
1
2
3
4
5
INPUT VOLTAGE (V)
Pin Description
PIN
MAX3205E
TQFN-EP
4, 5, 7,
12, 13, 15
1, 3, 6, 8,
9, 11, 14,
16
—
2
WLP
A2, A3, B1,
B3, C1, C2
—
MAX3207E
SOT23
1, 4
MAX3208E
μMAX
1, 4, 6, 9
TQFN-EP
4, 7, 12, 15
1, 3, 5, 6,
8, 9, 11,
13, 14, 16
—
2
I/O_
ESD-Protected Channel
NAME
FUNCTION
3, 6
2, 5, 7, 10
N.C.
No Connection. Not internally connected.
No Connection. The solder sphere is omitted from
this location (see the
Package Information
section).
Ground. Connect GND with a low-impedance
connection to the ground plane.
Power-Supply Input. Bypass V
CC
to GND with a
0.1μF ceramic capacitor as close to the device as
possible.
Exposed Pad (TQFN Only). Connect EP to GND.
B2
A1
—
2
—
3
N.C.
GND
10
—
C3
—
5
—
8
—
10
—
V
CC
EP
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3
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
MAX3205E/MAX3207E/MAX3208E
Detailed Description
The MAX3205E/MAX3207E/MAX3208E low-capacitance,
±15kV ESD-protection diode arrays with an integrated
transient voltage suppressor (TVS) clamp are suitable for
high-speed and general-signal ESD protection. Low
input capacitance makes these devices ideal for ESD
protection of signals in HDTV, PC monitors (DVI, HDMI),
PC peripherals (FireWire, USB 2.0), server interconnect
(PCI Express, InfiniBand), datacom, and interchassis
interconnect. Each channel consists of a pair of diodes
that steer ESD current pulses to V
CC
or GND. The
MAX3207E, MAX3208E, and MAX3205E are two, four,
and six channels (see the
Functional Diagram).
The MAX3205E/MAX3207E/MAX3208E are designed to
work in conjunction with a device’s intrinsic ESD pro-
tection. The MAX3205E/MAX3207E/MAX3208E limit the
excursion of the ESD event to below ±25V peak voltage
when subjected to the Human Body Model waveform.
When subjected to the IEC 61000-4-2 waveform and
Contact Discharge, the peak voltage is limited to ±60V.
The peak voltage is limited to ±100V when subjected to
Air-Gap Discharge. The device protected by the
MAX3205E/MAX3207E/MAX3208E must be able to
withstand these peak voltages, plus any additional volt-
age generated by the parasitic of the board.
A TVS is integrated into the MAX3205E/MAX3207E/
MAX3208E to help clamp ESD to a known voltage. This
helps reduce the effects of parasitic inductance on the
V
CC
rail by clamping V
CC
to a known voltage during an
ESD event. For the lowest possible clamp voltage dur-
ing an ESD event, placing a 0.1µF capacitor as close to
V
CC
as possible is recommended.
Functional Diagram
MAX3207E
MAX3208E
MAX3205E
V
CC
V
CC
V
CC
I/O1
I/O2
I/O1
I/O2
I/O3
I/O4
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
GND
GND
GND
4
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Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the
Layout Recommendations
section). A good layout reduces the parasitic series
inductance on the ground line, supply line, and protect-
ed signal lines. The MAX3205E/MAX3207E/MAX3208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
V
CC
. In an ideal circuit, the clamping voltage (V
C
) is
defined as the forward voltage drop (V
F
) of the protec-
tion diode, plus any supply voltage present on the cath-
ode.
For positive ESD pulses:
V
C
= V
CC
+ V
F
For negative ESD pulses:
V
C
= -V
F
The effect of the parasitic series inductance on the
lines must also be considered (Figure 1).
For positive ESD pulses:
d(I
ESD
)
⎞ ⎛
d(I
ESD
)
⎞
⎛
V
C
=
V
CC
+
V
F
(
D1
)
+ ⎜
L1 x
⎟
⎟ + ⎜
L2 x
⎝
dt
⎠ ⎝
dt
⎠
For negative ESD pulses:
⎛
d(I
ESD
)
⎞ ⎛
d(I
ESD
)
⎞ ⎞
⎛
V
C
= − ⎜
V
F
(
D2
)
+ ⎜
L1 x
⎟ + ⎜
L3 x
⎟
⎝
dt
⎠ ⎝
dt
⎠ ⎟
⎝
⎠
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 2). For example,
in a 15kV IEC 61000 Air-Gap Discharge ESD event, the
pulse current rises to approximately 45A in 1ns (di/dt =
45 x 10
9
). An inductance of only 10nH adds an addi-
tional 450V to the clamp voltage and represents
approximately 0.5in of board trace. Regardless of the
device’s specified diode clamp voltage, a poor layout
with parasitic inductance significantly increases the
effective clamp voltage at the protected signal line.
Minimize the effects of parasitic inductance by placing
the MAX3205E/MAX3207E/MAX3208E as close to the
connector (or ESD contact point) as possible.
A low-ESR 0.1µF capacitor is recommended between
V
CC
and GND in order to get the maximum ESD protec-
tion possible. This bypass capacitor absorbs the
charge transferred by a positive ESD event. Ideally, the
supply rail (V
CC
) would absorb the charge caused by a
positive ESD strike without changing its regulated
value. All power supplies have an effective output
impedance on their positive rails. If a power supply’s
effective output impedance is 1Ω, then by using V = I x
R, the clamping voltage of V
C
increases by the equa-
tion V
C
= I
ESD
x R
OUT
. A +8kV IEC 61000-4-2 ESD
event generates a current spike of 24A. The clamping
voltage increases by V
C
= 24A x 1Ω, or V
C
= 24V.
Again, a poor layout without proper bypassing increas-
es the clamping voltage. A ceramic chip capacitor
mounted as close as possible to the MAX3205E/
MAX3207E/MAX3208E V
CC
pin is the best choice for
this application. A bypass capacitor should also be
placed as close to the protected device as possible.
MAX3205E/MAX3207E/MAX3208E
where I
ESD
is the ESD current pulse.
POSITIVE SUPPLY RAIL
L2
I
100%
90%
I
PEAK
D1
L1
I/O_
PROTECTED
LINE
D2
10%
t
R
= 0.7ns to 1ns
L3
GROUND RAIL
30ns
60ns
t
Figure 1. Parasitic Series Inductance
Figure 2. IEC 61000-4-2 ESD Generator Current Waveform
5
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