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5962-9315706HXA

Description
SRAM Module, 256KX8, 45ns, CMOS, CDIP32,
Categorystorage    storage   
File Size112KB,22 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

5962-9315706HXA Overview

SRAM Module, 256KX8, 45ns, CMOS, CDIP32,

5962-9315706HXA Parametric

Parameter NameAttribute value
Reach Compliance Codeunknown
Maximum access time45 ns
Other featuresBATTERY BACK-UP OPERATION
JESD-30 codeR-CDIP-T32
JESD-609 codee0
memory density2097152 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of terminals32
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize256KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal locationDUAL
Base Number Matches1
REVISIONS
LTR
D
DESCRIPTION
Table I; Changed the max limit for I
CC
for device types 06 through 09
from 150 mA to 180 mA. Changed the max limit for I
CCDR
for device
types 06 through 09 from 6.4 mA to 7.0 mA. -sld
Added cage code 0EU86 fro device types 05 through 08. Figure 1;
case outline Y, changed dimension C (min) from 0.009 to 0.008
inches, dimension D (min) from 1.654 to 1.584 inches, dimension E
(max) from 0.604 to 0.605 inches and dimension Q (max) from 0.047
to 0.060 inches. Added a monolithic block diagram to figure 6. -sld
Added note to paragraph 1.2.2 and table I to regarding the 4
transistor design. Added thermal resistance ratings for all case
outlines to paragraph 1.3. Editorial changes throughout. -sld
Table I; Change the min limit for t
OH
as follows: For device types 01-
03 change from 15 ns to 3 ns. For device type 04 change from 5 ns to
3 ns. For device types 05-09 change from 3 ns to 0 ns. -gjc
DATE (YR-MO-DA)
98-06-22
APPROVED
K. A. Cottongim
E
99-11-01
Raymond Monnin
F
00-07-11
Raymond Monnin
G
02-04-02
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
G
15
G
16
G
17
G
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
G
19
G
20
G
1
G
2
G
3
G
4
G
5
G
6
G
7
G
8
G
9
G
10
G
11
G
12
G
13
G
14
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
POST OFFICE BOX 3990
COLUMBUS, OHIO 43216-5000
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, MEMORY, HYBRID AND
MONOLITHIC, DIGITAL, STATIC RANDOM
ACCESS MEMORY, CMOS, 256K x 8-BIT
DRAWING APPROVAL DATE
93-04-01
REVISION LEVEL
G
SIZE
A
SHEET
CAGE CODE
67268
1 OF
19
5962-93157
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E291-02
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