Integrated
Circuit
Systems, Inc.
ICS950508
Programmable Timing Control Hub™ for PII/III™
Recommended Application:
810/810E/815 and 815 B-Step type chipset
Output Features:
•
2 - CPUs @ 2.5V
•
13 - SDRAM @ 3.3V
•
3 - 3V66 @ 3.3V
•
8 - PCI @3.3V
•
1 - 24/48MHz@ 3.3V
•
1 - 48MHz @ 3.3V fixed
•
1 - REF @3.3V, 14.318MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2
C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
CPU Output Jitter: <250ps
•
IOAPIC Output Jitter: <500ps
•
48MHz, 3V66, PCI Output Jitter: <500ps
•
Ref Output Jitter. <1000ps
•
CPU Output Skew: <175ps
•
PCI Output Skew: <500ps
•
3V66 Output Skew <175ps
•
For group skew timing, please refer to the
Group Timing Relationship Table.
VDDREF
X1
X2
GND
GND
3V66_0
3V66_1
3V66_2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
*FS1/PCICLK1
1
*SEL24_48#/PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GND
Vtt_PWRGD/PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GND
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4 *
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GND
GND
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GND
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND
24_48MHz/FS2*
48MHZ/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GND
1
56-Pin 300-mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
ICS950508
48MHz
24_48MHz
REF0
CPU
DIVDER
2
CPUCLK (1:0)
SDRAM
DIVDER
12
SDRAM (11:0)
SDRAM_F
FS(4:0)
PD#
SEL24_48#
Vtt_PWRGD
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
IOAPIC
PCI
DIVDER
8
PCICLK (7:0)
3V66
DIVDER
3
3V66 (2:0)
0470E—04/06/05
Integrated
Circuit
Systems, Inc.
ICS950508
General Description
The
ICS950508
is a single chip clock solution for desktop designs using the 810/810E, 815 and 815 B-Step style chipset. It
provides all necessary clock signals for such a system.
The
ICS950508
is part of a whole new line of ICS clock generators and buffers called TCH™
(Timing
Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Pin Description
PIN NUMBER
1, 9, 10, 18, 25, 32, 33, 37, 45
2
3
4, 5, 14, 21, 28, 29, 36,
41, 49
8, 7, 6
11
PIN NAME
VDD
X1
X2
GND
3V66 (2:0)
PCICLK0
1
FS0
PCICLK1
1
12
FS1
13
20, 19, 17, 16, 15
SEL_24_48#
PCICLK2
1
PCICLK (7:3)
PD#
22
Vtt_PWRGD
23
24
34
35
38
48, 46, 47, 44, 43, 42, 40, 39,
31, 30, 27, 26
50
51, 52
53, 55
54
56
0470E—04/06/05
TYPE
PWR
IN
OUT
PWR
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
IN
3 . 3 V p ow e r s u p p l y
DESCRIPTION
Cr ystal input, has inter nal load cap (33pF) and feedback resistor
from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load cap
(33pF)
Ground pins for 3.3V supply
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock output, with Synchronous CPUCLKs
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3 . 3 V P C I c l o ck o u t p u t , w i t h S y n c h r o n o u s C P U C L K s
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Logic input to select output.
3 . 3 V P C I c l o ck o u t p u t , w i t h S y n c h r o n o u s C P U C L K s
3.3V PCI clock outputs, with Synchronous CPUCLKs
Asynchronous active low input pin used to power down the device
into a low power state. The inter nal clocks are disabled and the
V C O a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n
w i l l n o t b e g r e a t e r t h a n 3 m s.
This pin acts as a dual function input pin for Vtt_PWRGD and
PD# signal. When Vtt_PWRGD goes high the frequency select
w i l l b e l a t c h e d a t p ow e r o n ; t h e r e a f t e r t h e p i n i s a n a s y n c h r o n o u s
active low power down pin.
Clock pin for I
2
C circuitr y 5V tolerant
Data pin for I
2
C circuitr y 5V tolerant
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output for USB
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V 24_48MHz output, selectable through pin 13, default is
24MHz.
3 . 3 V S D R A M o u t p u t c a n b e t u r n e d o f f t h r o u g h I
2
C
3 . 3 V o u t p u t . A l l S D R A M o u t p u t s c a n b e t u r n e d o f f t h r o u g h I
2
C
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. Output frequency der ived from FS
p i n s.
2.5V power suypply for CPU, IOAPIC
2.5V clock outputs r unning at 16.67MHz.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V, 14.318MHz reference clock output.
IN
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
PWR
OUT
PWR
OUT
IN
OUT
SCLK
SDATA
FS3
48MHz
FS2
24_48MHz
SDRAM_F
SDRAM (11:0)
GNDL
CPUCLK (1:0)
VDDL
IOAPIC
FS4
REF0
1
2
Integrated
Circuit
Systems, Inc.
ICS950508
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page
.
0470E—04/06/05
3
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