5962-8959807MTX datasheet, PDF

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5962-8959807MTX: DescriptionStandard SRAM, 128KX8, 85ns, CMOS, CDFP32,; Categorystorage storage; File Size441KB，91 Pages; ManufacturerWhite Microelectronics

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5962-8959807MTX Overview

Standard SRAM, 128KX8, 85ns, CMOS, CDFP32,

5962-8959807MTX Parametric

Parameter Name	Attribute value
Reach Compliance Code	unknown
Maximum access time	85 ns
JESD-30 code	R-CDFP-F32
length	20.825 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.97 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.415 mm
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Add device type 41. Make corrections to case outline N, dimension b.

Add vendor CAGE 65786 as source of supply for device type 41.

Update boilerplate. Editorial changes throughout.

Add device types 42, 43, 44, 45, and 46. Editorial changes to pages

1, 3, 7-15. Update boilerplate. ksr

Added provisions to accommodate radiation-hardened devices.

Added device type 47 to drawing. glg

Corrected case outline 8 Figure 1 to show correct numbering of

terminals. Corrected Figure 2 Terminal connections. Corrected the

case outline Y Figure 1 to show the proper distance of E and E1.

Added note to Case outline Y Figure 1, to allow for bottom brazed

package as an alternative style to the side brazed package . Update

boilerplate. Editorial changes throughout. ksr

Changed the minimum value for the Q dimension on package T from

0.026 to 0.020 and removed footnote 12. Editorial changes

throughout.. ksr

Added device type 48 to drawing. ksr

Corrected typo on Figure 4 (Read Cycle). ksr

Vendor requested change in capacitance in Table I for devices 39 and

40 from 5 pF to 8 pF. ksr

DATE (YR-MO-DA)

97-03-26

APPROVED

Raymond Monnin

98-03-03

00-03-01

00-12-08

Raymond Monnin

02-12-19

Raymond Monnin

03-08-12

05-08-16

06-02-13

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Kenneth S. Rice

CHECKED BY

Raymond Monnin

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

APPROVED BY

Michael A. Frye

DRAWING APPROVAL DATE

89-04-21

REVISION LEVEL

MICROCIRCUIT, MEMORY, DIGITAL,

CMOS, 128K X 8 STATIC RANDOM

ACCESS MEMORY (SRAM) LOW POWER,

MONOLITHIC SILICON

SIZE

SHEET

CAGE CODE

67268

1 OF

5962-89598

5962-E261-06

DSCC FORM 2233

APR 97

ELECTRONICS INDUSTRIES ASSOCIATION (EIA)

JEDEC Standard EIA/JESD78

IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington,

VA 22201;

http://www.jedec.org.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the

text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations

unless a specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix C to this document.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as

specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device

class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table. The truth table shall be as specified on figure 3.

3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be

allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the

manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V

alternate test patterns shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance

with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.

3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection

only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass

the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor

testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements

as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The

electrical tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the

manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA

designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking

for device class M shall be in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required

in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate

of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103

(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for

this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-

38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-89598

SHEET

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