LH5P864
FEATURES
•
65,536
×
8 bit organization
•
Access time: 80 ns (MAX.)
•
Cycle time: 140 ns (MIN.)
•
Single +5 V power supply
•
Power consumption:
Operating: 440 mW (MAX.)
Standby (TTL level): 22 mW (MAX.)
Standby (CMOS level): 2.75 mW (MAX.)
•
Operating temperature: 0 to 70°C
•
TTL compatible I/O
•
512 refresh cycles/8 ms (MAX.)
•
Available for auto-refresh and
self-refresh modes
•
Package: 32-pin, 525-mil SOP
DESCRIPTION
The LH5P864 is a 512K-bit Pseudo-Static RAM or-
ganized as 65,536
×
8 bits. It is fabricated using sili-
con-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
CMOS 512K (64K
×
8) Pseudo-Static RAM
PIN CONNECTIONS
32-PIN SOP
TOP VIEW
TEST
NC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
NC
CE
2
R/W
A
13
A
8
A
9
A
11
OE/RFSH
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
5P864-1
Figure 1. Pin Connections for SOP Package
1
LH5P864
CMOS 512K (64K
×
8) Pseudo-Static RAM
16 GND
32 V
CC
A
0
12
A
1
11
A
2
10
A
3
9
A
4
8
A
5
7
A
6
A
7
A
8
A
9
6
5
27
26
A
0
- A
7
ROW
ADDRESS
BUFFER
SENSE
AMPS
I/O
SELECTOR
DATA
IN
BUFFER
13 I/O
0
14 I/O
1
15 I/O
2
17 I/O
3
18 I/O
4
19 I/O
5
20 I/O
6
DATA
OUT
BUFFER
21 I/O
7
V
BB
GENERATOR
A
8
- A
14
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
A
10
23
A
11
25
A
12
4
A
13
28
A
14
3
REFRESH
ADDRESS
COUNTER
EXT/INT
ADDRESS
MUX
ROW
DECODER
MEMORY
ARRAY
256K
MEMORY
ARRAY
256K
CE
1
22
CE
2
30
CLOCK
GENERATOR
TEST
1
1
REFRESH
CONTROLLER
REFRESH
TIMER
OE/
24
RFSH
R/W 29
5P864-2
Figure 2. LH5P864 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
14
R/W
OE/RFSH
CE
1
, CE
2
I/O
0
- I/O
7
Address input
Read/Write Enable input
Output Enable input/Refresh
input
Chip Enable input
Data input/output
V
CC
GND
Test
NC
Power Supply
Ground
Test Input
No Connection
2
CMOS 512K (64K
×
8) Pseudo-Static RAM
LH5P864
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on any pin
Output short circuit current
Power dissipation
Operating temperature
Storage temperature
V
T
I
O
P
D
Topr
Tstg
-1.0 to +7.0
50
600
0 to +70
-65 to +150
V
mA
mW
°C
°C
1
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
Input voltage
V
CC
V
IH
V
IL
4.5
2.4
-1.0
5.0
5.5
V
CC
+ 0.3
0.8
V
V
V
CAPACITANCE (T
A
= 0 to +70°C, f = 1MHz, V
CC
= 5.0 V
±10%)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
A
0
- A
14
Input capacitance
R/W, OE/RFSH
CE
1
, CE
2
TEST
1
Input/Output capacitance
I/O
0
- I/O
7
C
IN1
C
IN2
C
IN3
C
IN4
C
OUT1
8
8
8
10
10
pF
pF
pF
pF
pF
DC CHARACTERISTICS (T
A
= 0 to +70°C, V
CC
= 5.0 V
±10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Operating current
Standby current
Self refresh average current
Input leakage current
Output leakage current
Output HIGH voltage
Output LOW voltage
I
CC1
I
CC2
I
CC3
I
LI
I
LO
V
OH
V
OL
t
RC
= t
RC
(MIN.)
TTL input
CMOS input
TTL input
CMOS input
0 V
≤
V
IN
≤
6.5 V,
0 V except on test pins
0 V
≤
V
OUT
≤
V
CC
+ 0.3 V,
Outputs in High-Z state
I
OUT
= -1.0 mA
I
OUT
= 4.0 mA
-10
-10
2.4
80
4.0
0.5
4.0
0.5
10
10
mA
mA
mA
mA
mA
µA
µA
V
1, 2
1, 3, 5
1, 3, 6
1, 4, 5
1, 4, 6
0.4
V
NOTES:
1. Specified values are with outputs open.
2. I
CC1
depends on the cycle time.
3. CE
1
= CE
2
= V
IH
, OE/RFSH = V
IH
4. CE
1
= CE
2
= V
IH
, OE/RFSH = V
IL
5. CE
1
= CE
2
= V
CC
– 0.2 V, OE/RFSH = V
CC
– 0.2 V
6. CE
1
= CE
2
= V
CC
– 0.2 V, OE/RFSH = 0.2 V
3
LH5P864
CMOS 512K (64K
×
8) Pseudo-Static RAM
AC CHARACTERISTICS
1,2,3
(T
A
= 0 to +70°C, V
CC
= 5.0 V
±10%)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
R/W to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
Write enable to output in High-Z
OE setup time
OE hold time
OE lead time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write
Data setup time from CE
Data hold time from write
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto refresh)
Refresh precharge time (Auto refresh)
CE delay time from refresh precharge (Auto
refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh precharge (Self refresh)
NOTES:
1. In order to initialize the circuit, CE
1
, CE
2
and OE/RFSH should
be kept in V
IH
for 100
µs
after power-up and followed by at least
8 dummy cycles.
2. AC characteristics are measured at t
T
= 5 ns.
3. AC characteristics are measured at the following condition (see
figure at right).
4. Address is latched at the negative edge of CE
1
or CE
2
.
5. Measured with a load equivalent to 2TTL + 100 pF.
6. Data is latched at the positive edge of R/W or at the positive edge
of CE
1
or CE
2
.
t
RC
t
RMW
t
CE
t
P
t
AS
t
AH
t
RCS
t
RCH
t
CEA
t
OEA
t
CLZ
t
OLZ
t
WLZ
t
CHZ
t
OHZ
t
WHZ
t
OES
t
OEH
t
OEL
t
WCP
t
WCS
t
WCH
t
DSW
t
DSC
t
DHW
t
DHC
t
T
t
REF
t
FC
t
RFD
t
FAP
t
FP
t
FCE
t
FAS
t
FRS
140
205
80
50
0
20
0
0
80
30
20
0
0
25
25
25
10
10
10
30
30
50
30
30
0
0
3
130
50
30
30
160
8,000
160
8,000
35
8
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
6
6
6
6
5
5
4
4
INPUT
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
5P864-3
OUTPUT
Figure 3. AC Characteristics
4
CMOS 512K (64K
×
8) Pseudo-Static RAM
LH5P864
t
RC
t
P
V
IH
CE
1
V
IL
(OR CE
2
)
V
IH
CE
2
(OR CE
1
) V
IL
t
AS
t
AH
t
CE
t
P
A
0
- A
14
V
IH
V
IL
ADDRESS INPUT
t
OEH
t
OEL
t
OES
V
OE/RFSH V
IH
IL
t
RCS
V
IH
R/W V
IL
t
OEA
t
CEA
t
OLZ
t
CLZ
V
I/O
0
- I/O
7
V
OH
OL
t
CHZ
t
OHZ
t
RCH
VALID-DATA OUTPUT
5P864-4
Figure 4. Read Cycle
5
PCB Design
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