5962-8960901EA datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> 5962-8960901EA

5962-8960901EA: DescriptionHigh Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125; CategoryAnalog mixed-signal IC The signal circuit; File Size926KB，34 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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5962-8960901EA Overview

High Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125

5962-8960901EA Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Maker	Texas Instruments
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	not_compliant
ECCN code	EAR99
Factory Lead Time	6 weeks
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-GDIP-T16
JESD-609 code	e0
length	21.34 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/6 V
Certification status	Qualified
Filter level	MIL-STD-883
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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	5962-8960901EA	5962-8875701EA	CD54HC4046AF	CD54HC4046AF3A	CD54HCT4046AF3A	CD54HC4046A	CD54HCT4046A	CD74HC4046A	CD74HCT4046A
Description	High Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125	High Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125	High Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125	High Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125	High Speed CMOS Logic Phase-Locked-Loop with VCO 16-CDIP -55 to 125	CD54HC4046A High Speed CMOS Logic Phase-Locked-Loop with VCO	CD54HCT4046A High Speed CMOS Logic Phase-Locked-Loop with VCO	CD74HC4046A High Speed CMOS Logic Phase-Locked-Loop with VCO	CD74HCT4046A High Speed CMOS Logic Phase-Locked-Loop with VCO
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	-	-	-	-
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	-	-	-	-
Parts packaging code	DIP	DIP	DIP	DIP	DIP	-	-	-	-
package instruction	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3	-	-	-	-
Contacts	16	16	16	16	16	-	-	-	-
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	-	-	-	-
Factory Lead Time	6 weeks	1 week	6 weeks	6 weeks	6 weeks	-	-	-	-
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP	PHASE LOCKED LOOP	PHASE LOCKED LOOP	PHASE LOCKED LOOP	PHASE LOCKED LOOP	-	-	-	-
JESD-30 code	R-GDIP-T16	R-GDIP-T16	R-GDIP-T16	R-GDIP-T16	R-GDIP-T16	-	-	-	-
JESD-609 code	e0	e0	e0	e0	e0	-	-	-	-
length	21.34 mm	21.34 mm	21.34 mm	21.34 mm	21.34 mm	-	-	-	-
Number of functions	1	1	1	1	1	-	-	-	-
Number of terminals	16	16	16	16	16	-	-	-	-
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	-	-	-	-
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-	-	-	-
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	-	-	-	-
encapsulated code	DIP	DIP	DIP	DIP	DIP	-	-	-	-
Encapsulate equivalent code	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3	-	-	-	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	-	-
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	-	-	-	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	-
power supply	2/6 V	5 V	2/6 V	2/6 V	5 V	-	-	-	-
Certification status	Qualified	Qualified	Not Qualified	Not Qualified	Not Qualified	-	-	-	-
Maximum seat height	5.08 mm	5.08 mm	5.08 mm	5.08 mm	5.08 mm	-	-	-	-
Maximum supply voltage (Vsup)	6 V	5.5 V	6 V	6 V	5.5 V	-	-	-	-
Minimum supply voltage (Vsup)	2 V	4.5 V	2 V	2 V	4.5 V	-	-	-	-
Nominal supply voltage (Vsup)	3 V	5 V	3 V	3 V	5 V	-	-	-	-
surface mount	NO	NO	NO	NO	NO	-	-	-	-
technology	CMOS	CMOS	CMOS	CMOS	CMOS	-	-	-	-
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	-	-	-	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	-	-	-
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	-	-	-	-
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	-	-	-	-
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	-	-	-	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	-
width	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	-	-	-	-

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