INTEGRATED CIRCUITS
PCA9545
4-channel I
2
C switch with interrupt logic
and reset
Product data
Supersedes data of 2001 Nov 08
2002 Mar 28
Philips
Semiconductors
Philips Semiconductors
Product data
4-channel I
2
C switch with interrupt logic and reset
PCA9545
passed by the PCA9545. This allows the use of different bus
voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
A0 1
20 V
DD
19 SDA
18 SCL
17 INT
16 SC3
15 SD3
14 INT3
13 SC2
12 SD2
11 INT2
FEATURES
•
1-of-4 bi-directional translating switches
•
I
2
C interface logic; compatible with SMBus standards
•
4 active low interrupt inputs
•
Active low interrupt output
•
Active low reset input
•
2 address pins allowing up to 4 devices on the I
2
C bus
•
Channel selection via I
2
C bus, in any combination
•
Power up with all switch channels deselected
•
Low RDS
ON
switches
•
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
•
No glitch on power-up
•
Supports hot insertion
•
Low stand-by current
•
Operating power supply voltage range of 2.3 V to 5.5 V
•
5 V tolerant Inputs
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Package Offer: SO20, TSSOP20
DESCRIPTION
The PCA9545 is a quad bi-directional translating switch controlled
via the I
2
C bus. The SCL/SDA upstream pair fans out to four
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable control register. Four interrupt inputs,
INT0 to INT3, one for each of the downstream pairs, are provided.
One interrupt output, INT, acts as an AND of the four interrupt
inputs.
An active-LOW reset input allows the PCA9545 to recover from a
situation where one of the downstream I
2
C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I
2
C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
exceeds 100 mA
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
5 V buses
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A1 2
RESET 3
INT0 4
SD0 5
SC0 6
INT1 7
SD1 8
SC1 9
VSS 10
SW00762
Figure 1. Pin configuration
PIN DESCRIPTION
SYMBOL
A0
A1
RESET
INT0
SD0
SC0
INT1
SD1
SC1
V
SS
INT2
SD2
SC2
INT3
SD3
SC3
INT
SCL
SDA
V
DD
FUNCTION
Address input 0
Address input 1
Active low reset input
Active low interrupt input 0
Serial data 0
Serial clock 0
Active low interrupt input 1
Serial data 1
Serial clock 1
Supply ground
Active low interrupt input 2
Serial data 2
Serial clock 2
Active low interrupt input 3
Serial data 3
Serial clock 3
Active low interrupt output
Serial clock line
Serial data line
Supply voltage
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SO
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
PCA9545D
DRAWING NUMBER
SOT163-1
SOT360-1
20-Pin Plastic TSSOP
–40 to +85
°C
PCA9545PW
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 Mar 28
2
853-2302 27940
Philips Semiconductors
Product data
4-channel I
2
C switch with interrupt logic and reset
PCA9545
BLOCK DIAGRAM
PCA9545
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
V
SS
V
DD
RESET
POWER ON
RESET
SCL
INPUT
FILTER
I
2
C-BUS
CONTROL
A0
A1
SDA
INT[0–3]
INT LOGIC
INT
SW00758
Figure 2. Block diagram
2002 Mar 28
3
853-2302 27311
Philips Semiconductors
Product data
4-channel I
2
C switch with interrupt logic and reset
PCA9545
DEVICE ADDRESS
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9545 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
1
1
1
FIXED
0
0
A1 A0 R/W
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9545 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I
2
C bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
INT3 INT2 INT1 INT0
B3
B2
B1
B0
COMMAND
Channel 0
0
disabled
X
X
X
X
X
X
X
Channel 0
1
enabled
Channel 1
0
disabled
X
X
X
X
X
X
X
Channel 1
1
enabled
Channel 2
0
disabled
X
X
X
X
X
X
X
Channel 2
1
enabled
Channel 3
0
disabled
X
X
X
X
X
X
X
Channel 3
1
enabled
NOTE:
Several channels can be enabled at the same time.
Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are
disabled and channel 1 and 2 are enabled.
Care should be taken not to exceed the maximum bus capacity.
HARDWARE SELECTABLE
SW00893
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9545, which will be stored
in the control register. If multiple bytes are received by the
PCA9545, it will save the last byte received. This register can be
written and read via the I
2
C bus.
INTERRUPT BITS CHANNEL SELECTION BITS
(READ ONLY)
(READ/WRITE)
7
6
5
4
3
B3
2
B2
1
B1
0
B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
INT0
INT1
INT2
INT3
SW00949
INT3 INT2 INT1 INT0
Figure 4. Control Register
2002 Mar 28
4
853-2302 27311
Philips Semiconductors
Product data
4-channel I
2
C switch with interrupt logic and reset
PCA9545
INTERRUPT HANDLING
The PCA9545 provides 4 interrupt inputs, one for each channel, and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9545 and the interrupt output
will be driven LOW. The channel does not need to be active for
detection of the interrupt. A bit is also set in the control register.
Bits 4 – 7 of the control register correspond to channels 0 – 3 of the
PCA9545, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9545 and read the contents of the control
register to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9545 to select this
channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9545 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9545 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9545 are constructed such that
the V
DD
voltage can be used to limit the maximum voltage that will
be passed from one I
2
C bus to another.
V
pass
vs. V
DD
5.0
4.5
MAXIMUM
4.0
TYPICAL
3.5
V
pass
3.0
2.5
2.0
If unused, interrupt input(s) must be connected to V
DD
through a
pull-up resistor.
Table 2. Control Register Read — Interrupt
INT3
INT2
INT1
INT0
0
X
X
X
1
0
X
X
1
0
X
1
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B3
B2
B1
B0
COMMAND
No interrupt
on channel 0
Interrupt on
channel 0
No interrupt
on channel 1
Interrupt on
channel 1
No interrupt
on channel 2
Interrupt on
channel 2
No interrupt
on channel 3
Interrupt on
channel 3
1.5
1.0
2.0
2.5
3.0
3.5
4.0
V
DD
4.5
MINIMUM
5.0
5.5
SW00820
Figure 5. V
pass
voltage vs. V
DD
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9545 to act as a voltage translator, the V
pass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
pass
should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V
pass
(max.) will be at 2.7 V when the
PCA9545 supply voltage is 3.5 V or lower so the PCA9545 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262
PCA954X
family of I
2
C/SMBus multiplexers and switches.
NOTE:
Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of t
WL
, the PCA9545 will reset its registers and I
2
C state
machine and will deselect all channels. The RESET input must be
connected to V
DD
through a pull-up resistor.
2002 Mar 28
5
853-2302 27311
MCU
京公网安备 11010802033920号
EEWORLD
