54F74LMQB datasheet, PDF - EEWORLD Datasheet

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54F74LMQB: DescriptionD Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, CQCC20, CERAMIC, LCC-20; Categorylogic logic; File Size152KB，8 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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54F74LMQB Overview

D Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, CQCC20, CERAMIC, LCC-20

54F74LMQB Parametric

Parameter Name	Attribute value
package instruction	QCCN,
Reach Compliance Code	unknown
series	F/FAST
JESD-30 code	S-CQCC-N20
length	8.89 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	1
Number of functions	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	SQUARE
Package form	CHIP CARRIER
propagation delay (tpd)	10.5 ns
Maximum seat height	1.905 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Trigger type	POSITIVE EDGE
width	8.89 mm
minfmax	80 MHz
Base Number Matches	1

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54F 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

December 1994

54F 74F74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The ’F74 is a dual D-type flip-flop with Direct Clear and Set

inputs and complementary (Q Q) outputs Information at the

input is transferred to the outputs on the positive edge of

the clock pulse Clock triggering occurs at a voltage level of

the clock pulse and is not directly related to the transition

time of the positive-going pulse After the Clock Pulse input

threshold voltage has been passed the Data input is locked

out and information present will not be transferred to the

outputs until the next rising edge of the Clock Pulse input

Asynchronous Inputs

LOW input to S

sets Q to HIGH level

LOW input to C

sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C

and S

makes both Q and Q HIGH

Features

Guaranteed 4000V minimum ESD protection

Commercial

74F74PC

Military

Package

Number

N14A

Package Description

14-Lead (0 300 Wide) Molded Dual-In-Line

14-Lead Ceramic Dual-In-Line

14-Lead (0 150 Wide) Molded Small Outline JEDEC

14-Lead (0 300 Wide) Molded Small Outline EIAJ

14-Lead Cerpack

20-Lead Ceramic Leadless Chip Carrier Type C

54F74DM (Note 2)

74F74SC (Note 1)

74F74SJ (Note 1)

54F74FM (Note 2)

54F74LM (Note 2)

J14A

M14A

M14D

W14B

E20A

Note 1

Devices also available in 13 reel Use Suffix

SCX

Note 2

Military grade device with environmental and burn-in processing Use suffix

DMQB FMQB and LMQB

Logic Symbols

IEEE IEC

TL F 9469 – 6

TL F 9469–3

TL F 9469 – 4

TRI-STATE is a registered trademark of National Semiconductor Corporation

1995 National Semiconductor Corporation

TL F 9469

RRD-B30M75 Printed in U S A

54F74LMQB Related Products

	54F74LMQB	54F74DMQB	54F74FMQB
Description	D Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, CQCC20, CERAMIC, LCC-20	D Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14	D Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, CDFP14, CERPACK-14
package instruction	QCCN,	DIP,	DFP,
Reach Compliance Code	unknown	unknown	unknown
series	F/FAST	F/FAST	F/FAST
JESD-30 code	S-CQCC-N20	R-CDIP-T14	R-CDFP-F14
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of digits	1	1	1
Number of functions	2	2	2
Number of terminals	20	14	14
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C
Output characteristics	3-STATE	3-STATE	3-STATE
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN	DIP	DFP
Package shape	SQUARE	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	FLATPACK
propagation delay (tpd)	10.5 ns	10.5 ns	10.5 ns
Maximum seat height	1.905 mm	5.08 mm	2.032 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	YES	NO	YES
technology	TTL	TTL	TTL
Temperature level	MILITARY	MILITARY	MILITARY
Terminal form	NO LEAD	THROUGH-HOLE	FLAT
Terminal pitch	1.27 mm	2.54 mm	1.27 mm
Terminal location	QUAD	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	8.89 mm	7.62 mm	6.2865 mm
minfmax	80 MHz	80 MHz	80 MHz
Base Number Matches	1	1	1
length	8.89 mm	19.43 mm	-

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