54F 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop
December 1994
54F 74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The ’F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q Q) outputs Information at the
input is transferred to the outputs on the positive edge of
the clock pulse Clock triggering occurs at a voltage level of
the clock pulse and is not directly related to the transition
time of the positive-going pulse After the Clock Pulse input
threshold voltage has been passed the Data input is locked
out and information present will not be transferred to the
outputs until the next rising edge of the Clock Pulse input
Asynchronous Inputs
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial
74F74PC
Military
Package
Number
N14A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F74DM (Note 2)
74F74SC (Note 1)
74F74SJ (Note 1)
54F74FM (Note 2)
54F74LM (Note 2)
J14A
M14A
M14D
W14B
E20A
Note 1
Devices also available in 13 reel Use Suffix
e
SCX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9469 – 6
TL F 9469–3
TL F 9469 – 4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9469
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9469– 1
TL F 9469 – 2
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 10
10 30
10 30
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
1 8 mA
20
mA
b
1 8 mA
b
1 mA 20 mA
D
1
D
2
CP
1
CP
2
C
D1
C
D2
S
D1
S
D2
Q
1
Q
1
Q
2
Q
2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
Truth Table
Inputs
S
D
L
H
L
H
H
H
C
D
H
L
L
H
H
H
CP
X
X
X
L
L
L
D
X
X
X
h
l
X
Outputs
H (h)
e
HIGH Voltage Level
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
L (l)
e
LOW Voltage Level
X
e
Immaterial
Q
0
e
Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one
setup time prior to the LOW-to-HIGH clock transition
Logic Diagram
TL F 9469 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
30 mA to
a
5 0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
b
0 5V to V
CC
Standard Output
b
0 5V to
a
5 5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
b
60
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
20 mA
I
OL
e
20 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V (D CP)
V
IN
e
0 5V (C
D
S
D
)
V
OUT
e
0V
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
25
25
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 6
b
1 8
b
150
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
V
mA
mA
mA
V
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
10 5
16 0
3
AC Electrical Characteristics
74F
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
100
38
44
32
35
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
125
53
62
46
70
68
80
61
90
Max
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
80
38
44
32
35
85
10 5
80
11 5
Max
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
100
38
44
32
35
78
92
71
10 5
Max
MHz
ns
ns
Units
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
Setup Time HIGH or LOW
D
n
to CP
n
Hold Time HIGH or LOW
D
n
to CP
n
CP
n
Pulse Width
HIGH or LOW
C
Dn
or S
Dn
Pulse Width
LOW
Recovery Time
C
Dn
or S
Dn
to CP
20
30
10
10
40
50
40
20
Max
54F
T
A
V
CC
e
Mil
Min
30
40
20
20
40
60
40
30
Max
74F
T
A
V
CC
e
Com
Min
20
30
10
10
40
50
40
20
ns
ns
ns
Max
Units
ns
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
74
S
C
X
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
X
e
Devices shipped in 13 reel
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
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