GT-482xx
Galileo
GT-48212 / GT-48208 / GT-48207
Advanced Switched Ethernet Controllers for 10+10/100 BaseX
Preliminary
Revision 1.2
1/27/99
Please contact Galileo Technology for possible
updates before finalizing a design.
FEATURES
• Single-chip Switched Ethernet Controllers for
10 and 10/100Base-X
- Provides packet switching functions between
eight or 12 Ethernet ports and two Auto-
Negotiated on-chip Fast Ethernet ports
- Switch expansion via Fast MII port
• Direct support for packet buffering
- 1Mbyte: using one device - 256Kx32-bit
Synchronous graphics RAM (SGDRAM)
- 4Mbyte: using two devices - 1Mx16bit SDRAM
- Up to 2K buffers, 1536-bytes each, dynamically
allocated to the receive queues and CPU
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
• Three versions for different cost/performance
points
- GT-48212: 12 10BaseT ports, two 100BaseX
ports and advanced management features
- GT-48208: eight 10BaseT ports, two 100BaseX
ports and advanced management features
- GT-48207: eight 10BaseT ports, two 100BaseX
ports with no management features
• High observability LED interface
- Three pin serial LED interface for additional
status information per port
• Advanced address recognition on-chip
- Intelligent address recognition mechanism
enables forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Multicast address support in Address Table
- Broadcast storm filtering
• Low-cost 32-bit CPU interface for
management
- Glueless interface to IDT 3041, Motorola
ColdFire, Intel i960®R/Jx CPUs, and GT-641xx
controllers.
- Simple interface to other 32/64-bit CPUs
• Extensive network management support
- Repeater MIB counters allowing implementation
of four RMON groups
- Hardware assist for Spanning Tree algorithm
- CPU access to Address Table
- CPU Query - Ability to read the information from
the Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
• Management CPU not required
- Allows for cost sensitive unmanaged designs
• Eight or Twelve 802.3 compliant Ethernet
ports
- 10Mbps Half-Duplex or 20Mbps Full-Duplex
- Serial mode selectable per port: 10Base-T or FL
• Port locking for security
• Automatic address aging support
• Priority queuing based on MAC address or
802.1Q tag
• Port and MAC address based VLAN
• IP Multicast support
• Flexible software or hardware intervention in
packet routing decisions
• Packet sampling management technology
• Two Fast Ethernet Media Access Controllers
-
-
-
-
-
Direct Interface to MII
Half/Full Duplex Support
IEEE 802.3 100Base-TX, T4, and FX compatible
Full MII Management Support (MDC/MDIO)
Auto-Negotiation supported through MII
Interface
• Flow Control on all ports
- Standard 802.3x flow control for Full Duplex
mode
- Back pressure for Half Duplex mode
www.galileoT.com
info@galileoT.com
Tel: 408-367-1400
Fax: 408-367-1401
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
- Takes “snapshots” of packets and counters at
programmable intervals
- Allows for the implementation of HP-EASE or
sampled RMON with low-cost CPUs
• 3.3V with 5V tolerant I/Os
• 208 pin PQFP package
• 12 General Purpose Output pins (LEDs, etc.)
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
Block Diagram of Typical Managed Switch
( T w o 1 0 0 M b i t P o r t s + 1 2 1 0 M b i t P o r t s)
CPU
(optional)
CPU Bus (when CPU present)
SDRAM
GT-48212
10BaseT Filters
100BaseTX
PHY/XCVR
12 x 10BaseT
2 x 100BaseTX
Block Diagram of Typical Managed Switch
( T w o 1 0 0 M b i t P o r t s + 2 4 1 0 M b i t P o r t s)
CPU
(optional)
CPU Bus (when CPU present)
SDRAM
GT-48212
FAST MII
GT-48212
SDRAM
10BaseT Filters
100BaseTX
PHY/XCVR
10BaseT Filters
100BaseTX
PHY/XCVR
12 x 10BaseT
1 x 100BaseTX
12 x 10BaseT
1 x 100BaseTX
2
Revision 1.2
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
Table of Contents
1.
General Description ..................................................................................................... 9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
Fast Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flow Control and Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Synchronous GRAM/DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IP Multicast and VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Priority Queueing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Network Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Differences Between the GT-48212, GT-48208 and GT-48207 . . . . . . . . . . . . . . . . . . . 12
Pin Functions and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packet Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packet Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
20
20
20
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
2.
3.
Pinout .......................................................................................................................... 13
2.1
3.1
3.2
3.3
3.4
3.5
Galaxy Family Overview ............................................................................................ 19
4.
5.
Microarchitectural Overview ..................................................................................... 21
Buffers and Queues ................................................................................................... 23
5.1
5.2
Rx Buffer Threshold Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Head-of-Line Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Forwarding Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Learning Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Locked Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Entry Update and Query from CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Recognition Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding a Unicast Packet to a Local Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding a Multicast Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding a Packet to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding a Packet from the CPU to the GT-482xx . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intervention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGMP Packet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tx Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
27
28
28
30
31
31
31
33
33
33
34
35
35
35
36
6.
MAC Address Table ................................................................................................... 26
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7.
Packet Forwarding ..................................................................................................... 33
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Revision 1.2
3
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
8.
Fast Ethernet Interfaces ............................................................................................ 37
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
10/100 MII Compatible Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Backoff Algorithm Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Blinder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Inter-Packet Gap (IPG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10/100 Mbps MII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10/100 Mbps MII Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10/100 Mbps Full-duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Illegal Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Partition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
802.1q VLAN Tagging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MII Management Interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Link Detection and Link Detection Bypass (ForceLinkPass). . . . . . . . . . . . . . . . . . . . . . 43
Using the MII Interfaces to Connect Two (or More) Galaxy Devices . . . . . . . . . . . . . . . . 44
Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Illegal Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Duplex Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Backoff Algorithm Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Manchester Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Link Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data Blinder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Inter-Packet Gap (IPG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Partition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
802.1q VLAN Tagging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Serial Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Physical Interface Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Serial Link Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
9.
Ethernet (10Mbps) Interfaces .................................................................................... 45
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
10.
11.
Enabling/Disabling Ports........................................................................................... 48
Network Management Support ................................................................................. 49
11.1
11.2
11.3
11.4
Repeater MIB Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Monitoring (Sniffer) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Spanning Tree (BPDU) Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Broadcast Storm Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Packet Sampling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EASE Functionality on the GT-482xx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Ease Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EASE Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Sampled Packet Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.
Packet Sampling Technology (HP-EASE) ................................................................ 51
12.1
12.2
12.3
12.4
12.5
4
Revision 1.2
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
12.6 Error Source Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.7 Enabling/Disabling EASE Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.
LED Support ............................................................................................................... 54
13.1
13.2
13.3
13.4
LED Indications Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed LED Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Signal Timing Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
54
56
57
GALILEO TECHNOLOGY CONFIDENTIAL -- DO NOT REPRODUCE
14.
15.
Interrupts .................................................................................................................... 65
RESET Configuration................................................................................................. 66
15.1 Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
15.2 Configuration Input Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.
CPU Hardware Interface and Address Mapping...................................................... 69
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
Register and Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Interface Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the CPU Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT-482xx Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Interface Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Interface Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
69
70
70
70
71
79
79
17.
SDRAM Interface ........................................................................................................ 80
17.1 DRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.2 DRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
18.
Register Tables .......................................................................................................... 81
18.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
18.2 Port MIB Counters (14 Blocks), Offset (start): 0x600, 0xA00, 0xE00, 0x1200 . . . . . . . 107
19.
GT-482xx Pinout Differences .................................................................................. 112
19.1 Pinout Differences between GT-48207, GT-48208, and GT-48212 Devices . . . . . . . .
19.2 Using a GT-48212 in a GT-48208/7 Socket: Disabling Unused Ethernet Ports . . . . . .
19.3 Using a GT-48212 or GT-48208 in a GT-48207 Socket: Disabling Unused
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4 CClk in an Unmanaged System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
112
112
113
20.
21.
22.
23.
24.
GT-482xx Pinout Tables, 208-PQFP ....................................................................... 114
DC Characteristics - PRELIMINARY/SUBJECT TO CHANGE ) .......................... 120
21.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
AC Timing - TARGET/SUBJECT TO CHANGE....................................................... 122
Packaging ................................................................................................................. 127
Document History .................................................................................................... 129
Appendix A ....................................................................................................................... 135
Revision 1.2
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Microcontroller MCU
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