FAST CMOS 18-BIT
REGISTER
Integrated Device Technology, Inc.
IDT54/74FCT16823AT/BT/CT/ET
IDT54/74FCT162823AT/BT/CT/ET
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
–
Typical t
SK
(o) (Output Skew) < 250ps
– Low input and output leakage
≤1µA
(max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– V
CC
= 5V
±10%
• Features for FCT16823AT/BT/CT/ET:
– High drive outputs (-32mA I
OH
, 64mA I
OL
)
– Power off disable outputs permit “live insertion”
– Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25°C
• Features for FCT162823AT/BT/CT/ET:
– Balanced Output Drivers:
±24mA
(commercial),
±16mA
(military)
– Reduced system switching noise
– Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25°C
DESCRIPTION:
The FCT16823AT/BT/CT/ET and FCT162823AT/BT/CT/
ET 18-bit bus interface registers are built using advanced,
dual metal CMOS technology. These high-speed, low-power
registers with clock enable (x
CLKEN
) and clear (x
CLR
) con-
trols are ideal for parity bus interfacing in high-performance
synchronous systems. The control inputs are organized to
operate the device as two 9-bit registers or one 18-bit register.
Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise mar-
gin.
The FCT16823AT/BT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162823AT/BT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times – reduc-
ing the need for external series terminating resistors. The
FCT162823AT/BT/CT/ET are plug-in replacements for the
FCT16823AT/BT/CT/ET and ABT16823 for on-board inter-
face applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
CLR
1
CLK
1
CLKEN
2
OE
2
CLR
2
CLK
2
CLKEN
R
C
D
1
D
1
1
Q
1
2
D
1
R
C
D
2
Q
1
TO 8 OTHER CHANNELS
2772 drw 01
TO 8 OTHER CHANNELS
2772 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2772/8
5.16
1
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET
FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
CLR
1
OE
1
Q
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1 43
SO56-2
SO56-3 42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
CLK
1
CLKEN
1
D
1
1
CLR
1
OE
1
Q
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CERPACK
TOP VIEW
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
CLK
1
CLKEN
1
D
1
GND
1
Q
2
1
Q
3
GND
1
D
2
1
D
3
GND
1
Q
2
1
Q
3
GND
1
D
2
1
D
3
V
CC
1
Q
4
1
Q
5
1
Q
6
V
CC
1
D
4
1
D
5
1
D
6
V
CC
1
Q
4
1
Q
5
1
Q
6
V
CC
1
D
4
1
D
5
1
D
6
GND
1
Q
7
1
Q
8
1
Q
9
2
Q
1
2
Q
2
2
Q
3
GND
1
D
7
1
D
8
1
D
9
2
D
1
2
D
2
2
D
3
GND
1
Q
7
1
Q
8
1
Q
9
2
Q
1
2
Q
2
2
Q
3
GND
1
D
7
1
D
8
1
D
9
2
D
1
2
D
2
2
D
3
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
GND
2
Q
9
2
OE
2
CLR
GND
2
D
9
2
CLKEN
2
CLK
GND
2
Q
9
2
OE
2
CLR
GND
2
D
9
2
CLKEN
2
CLK
SSOP/
TSSOP/TVSOP
TOP VIEW
2772 drw 03
2772 drw 04
5.16
2
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET
FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
xDx
xCLK
x
CLKEN
x
CLR
x
OE
xQx
Description
Data inputs
Clock Inputs
Clock Enable Inputs (Active LOW)
Asynchronous clear Inputs
(Active LOW)
Output Enable Inputs (Active LOW)
3-State Outputs
2772 tbl 01
FUNCTION TABLE
(1)
x
OE
H
L
L
H
H
L
L
x
CLR
X
L
H
H
H
H
H
Inputs
x
CLKEN
X
X
H
L
L
L
L
xCLK
X
X
X
↑
↑
↑
↑
xDx
X
X
X
L
H
L
H
Outputs
xQx Function
Z
L
Q
(2)
Z
Z
L
H
High Z
Clear
Hold
Load
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
V
TERM(2)
Terminal Voltage with Respect to –0.5 to +7.0
GND
V
TERM(3)
Terminal Voltage with Respect to
–0.5 to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
°C
mA
NOTES:
2772 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level before indicated steady-state input conditions were estab-
lished.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max. Unit
6.0
pF
8.0
pF
2772 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
2772 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
5.16
3
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET
FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±
10%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
Min.
2.0
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–
0.7
–
140
Max.
—
Unit
V
V
µA
0.8
±1
±1
±1
±1
±1
±1
–
1.2
–
225
—
µA
V
mA
mV
µA
100
5
V
CC
= Max., V
IN
= GND or V
CC
500
2772 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16823T
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –3mA
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
I
OL
= 48mA MIL.
I
OL
= 64mA COM'L.
≤
4.5V
Min.
–50
2.5
2.4
2.0
—
—
Typ.
(2)
—
Max.
–
180
—
—
—
0.55
Unit
mA
V
V
V
V
3.5
3.5
3.0
0.2
—
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
±
1
µ
A
2772 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162823T
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
2772 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
5.16
4
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET
FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
x
OE
= x
CLKEN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
x
OE
= x
CLKEN
= GND
at fi = 5MHz
50% Duty Cycle
One Bit Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
x
OE
= x
CLKEN
= GND
at fi = 2.5MHz
50% Duty Cycle
Eighteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
0.5
75
Max.
1.5
120
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.8
1.7
mA
V
IN
= 3.4V
V
IN
= GND
—
1.3
3.2
V
IN
= V
CC
V
IN
= GND
—
4.2
7.1
(5)
V
IN
= 3.4V
V
IN
= GND
—
9.2
22.1
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
2772 tbl 08
5.16
5
Power technology
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