HD342
ADP I
SRAM
42o
5 Volt x8 Asynchronous Dual-Port Static RAM
Memory Configuration
4K x 8
Device
HD342
Key Features:
•
•
•
•
•
•
•
•
Industry leading asynchronous Dual-Port Static RAM (up to 15ns)
Simultaneous memory access through two ports
TTL compatible; 5V power supply
Supports semaphore arbitration schemes
Available packages: 52 – pin Plastic Lead Chip Carrier (PnLCC), 64 – pin Thin Quad Flat Pack (TQFP)
(0
°
C to 70
°
C) Commercial operating temperature available for access time of 15ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with conventional dual-port devices including IDT 71342 and Cypress CY7C1342
Product Description:
HBA’s Asynchronous Dual-Port (ADP I) Static RAM offers industry leading 0.25um process technology and 4K x 8 memory
configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous,
asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory
using the depth and width expansion features.
These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such
as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.
5HD083A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product
specifications subject to change without notice.
PRELIMINARY
Page 1 of 14
HD342
ADP I
SRAM
Block D iagram of Asynchronous D ual Port Static R AM
4K X 8
OE
L
CE
L
R /W
L
OE
R
CE
R
R / W
R
I/O
0 -7 L
I/O
Control
I/O
Control
I/O
0-7 R
A
1 1 L
A
0 L
Address
Decoder
SRAM
Address
Decoder
A
1 1 R
A
0 R
OE
L
CE
L
R / W
L
SEM
L
Semaphore
Logic
OE
R
CE
R
R /
W
R
SEM
R
Figure 1. Device Architecture
5HD083A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product
specifications subject to change without notice.
PRELIMINARY
Page 2 of 14
HD342
ADP I
SRAM
SEM
L
VCC
SEM
R
R/W
L
R/W
R
A
11R
A
10L
A
11L
NC
NC
NC
CE
R
A
10R
51
CE
L
NC
50
Index
64
63
62
61
60
59
58
57
56
55
54
53
52
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
A
7L
A
8L
A
9L
NC
I/O
0L
I/O
1L
I/O
2L
49
NC
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
48
47
46
45
44
43
42
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
A
7R
A
8R
A
9R
NC
NC
I/O
7R
I/O
6R
TQFP - 64 (Drw No: PF-01A; Order code: PF)
Top View
41
40
39
38
37
36
35
34
33
GND
I/O
3L
NC
NC
NC
I/O
0R
I/O
1R
I/O
2R
I/O
3R
NC
I/O
4R
SEM
L
SEM
R
R/W
R
R/W
L
OE
L
CE
L
Index
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
6
5
4
3
2
1
52
51
50
49
A
11R
48
A
10R
47
46
45
44
43
42
41
A
10L
A
11L
Vcc
CE
R
I/O
5R
I/O
4L
I/O
5L
I/O
6L
I/O
7L
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
PLCC - 52 (Drw No: J-01A; Order code: J)
Top View
40
39
38
37
36
35
34
22
23
24
25
26
27
28
29
30
31
32
33
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
Figure 2. Device Pin-Out
I/O
6R
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
5HD083A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product
specifications subject to change without notice.
PRELIMINARY
Page 3 of 14
HD342
ADP I
SRAM
Left Port
_____
Right Port
CE
R
R/W
R
OE
R
A
0R-11R
I/O
7R – 0R
SEM
R
Vcc
________
_____
____
_____
Name
Chip Enable
Read / Write Enable
Output Enable
Address
Data Inputs / Outputs
Semaphore Enable
Power
Ground
Symbol
Rating
Terminal Voltage with
respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Com & Ind
-0.5 to + 7.0
-55 to +125
-65 to +150
50
Unit
V
°
CE
L
R/W
L
OE
L
A
0L-11L
I/O
7L – 0L
SEM
L
GND
________
_____
____
V
TERM
T
BIAS
T
STG
I
OUT
NOTES:
C
C
°
mA
Table 1. Pin Descriptions
Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended
period of operation is outside this range. Standard operation should fall within the Recommended
Operating Conditions
.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Commercial Temperature
Min.
4.5
0
2.2
-
0
-
-
2.4
-
Industrial Temperature
Min.
4.5
0
2.2
-
-40
-
-
2.4
-
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
-
0.8
70
5
5
-
0.4
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
-
0.8
85
5
5
-
0.4
Unit
Recommended Operating Conditions
V
CC
GND
Supply Voltage Com’l/Ind’l
Supply Voltage
Input High Voltage Com’l/Ind’l
Input Low Voltage Com’l/Ind’l
Operating Temperature
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, IOH=-4mA
Output Logic “0” Voltage, IOL = 4mA
V
V
V
V
°
V
IH
V
IL
T
A
I
LI
(1)
I
LO
V
OH
V
OL
C
DC Electrical Characteristics
µA
µA
V
V
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
Input Capacitance
C
IN(2)
Output Capacitance
C
OUT(2)
NOTES:
Conditions
(3)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
1. At Vcc < 2.0V, input leakage is undefined.
2. This parameter is determined by device characterization but is not production tested.
3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V.
5HD083A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product
specifications subject to change without notice.
PRELIMINARY
Page 4 of 14
HD342
ADP I
SRAM
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD34L15
Typ.
Max.
220
-
60
-
130
-
4.0
-
125
-
HD34L25
Typ.
160
160
25
25
95
95
0.2
0.2
95
95
Unit
Max.
180
190
40
50
110
120
4.0
mA
10
100
115
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
160
-
25
-
105
-
0.2
-
100
-
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
NOTES:
1.
2.
1.
2.
At f=f
MAX
, address and control lines, except Output Enable, are cycling at the maximum frequency read cycle of 1/trc, and using AC Test Conditions of input level of GND
to 3V.
f = 0 means no address or control lines change.
Vcc = 5V, tA = +25C for Typ and is not production tested. Vcc dc = 100mA (Typ)
Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port.
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD34L35
Typ.
Max.
160
-
30
-
100
-
4
-
90
-
HD34L55
Typ.
140
-
25
-
75
-
0.2
-
75
-
Unit
Max.
160
-
30
-
100
-
4
mA
-
90
-
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
150
-
25
-
85
-
0.2
-
85
-
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
5HD083A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product
specifications subject to change without notice.
PRELIMINARY
Page 5 of 14
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