EEWORLDEEWORLDEEWORLD

Part Number

Search

935289545118

Description
OR Gate
Categorylogic    logic   
File Size202KB,15 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric Compare View All

935289545118 Overview

OR Gate

935289545118 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionTSSOP,
Reach Compliance Codecompliant
seriesAHC/VHC/H/U/V
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length5 mm
Logic integrated circuit typeOR GATE
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)14.5 ns
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm
Base Number Matches1

935289545118 Preview

Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
74VHC32; 74VHCT32
Quad 2-input OR gate
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC32; 74VHCT32 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74VHC32; 74VHCT32 provide the 2-input OR function.
2. Features
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
N
The 74VHC32 operates with CMOS input level
N
The 74VHCT32 operates with TTL input level
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74VHC32D
74VHCT32D
74VHC32PW
74VHCT32PW
74VHC32BQ
74VHCT32BQ
−40 °C
to +125
°C
DHVQFN14
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74VHC32; 74VHCT32
Quad 2-input OR gate
4. Functional diagram
1
2
≥1
3
4
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
5
≥1
6
2Y
6
9
10
≥1
8
3Y
8
12
13
4Y
11
≥1
11
mna242
mna243
Fig 1. Logic symbol
Fig 2. IEC logic symbol
A
Y
B
mna241
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74VHC32
74VHCT32
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aak054
74VHC32
74VHCT32
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
terminal 1
index area
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
1A
1
001aak055
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
74VHC_VHCT32_1
Fig 5. Pin configuration DHVQFN14
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 13 August 2009
2 of 14
NXP Semiconductors
74VHC32; 74VHCT32
Quad 2-input OR gate
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Function table
[1]
Output
nB
L
H
X
nY
L
H
H
74VHC_VHCT32_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 13 August 2009
3 of 14
NXP Semiconductors
74VHC32; 74VHCT32
Quad 2-input OR gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
74VHC32
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
74VHCT32
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 4.5 V to 5.5 V
4.5
0
0
−40
-
5.0
-
-
+25
-
5.5
5.5
V
CC
+125
20
V
V
V
°C
ns/V
2.0
0
0
−40
-
-
5.0
-
-
+25
-
-
5.5
5.5
V
CC
+125
100
20
V
V
V
°C
ns/V
ns/V
Operating conditions
Conditions
Min
Typ
Max
Unit
Symbol Parameter
74VHC_VHCT32_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 13 August 2009
4 of 14

935289545118 Related Products

935289545118 74VHCT32PW 74VHCT32D 74VHCT32BQ 74VHC32BQ 74VHC32D 74VHC32PW 935289548118
Description OR Gate OR Gate OR Gate OR Gate OR Gate OR Gate OR Gate OR Gate
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to conform to
package instruction TSSOP, TSSOP, SOP, HVQCCN, HVQCCN, SOP, TSSOP, TSSOP,
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
series AHC/VHC/H/U/V AHCT/VHCT/VT AHCT/VHCT/VT AHCT/VHCT/VT AHC/VHC/H/U/V AHC/VHC/H/U/V AHC/VHC/H/U/V AHCT/VHCT/VT
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PQCC-N14 R-PQCC-N14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609 code e4 e4 e4 e4 e4 e4 e4 e4
length 5 mm 5 mm 8.65 mm 3 mm 3 mm 8.65 mm 5 mm 5 mm
Logic integrated circuit type OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE
Humidity sensitivity level 1 1 1 1 1 1 1 1
Number of functions 4 4 4 4 4 4 4 4
Number of entries 2 2 2 2 2 2 2 2
Number of terminals 14 14 14 14 14 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP SOP HVQCCN HVQCCN SOP TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd) 14.5 ns 10 ns 10 ns 10 ns 14.5 ns 14.5 ns 14.5 ns 10 ns
Maximum seat height 1.1 mm 1.1 mm 1.75 mm 1 mm 1 mm 1.75 mm 1.1 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 2 V 4.5 V 4.5 V 4.5 V 2 V 2 V 2 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING GULL WING GULL WING NO LEAD NO LEAD GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 1.27 mm 0.5 mm 0.5 mm 1.27 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL QUAD QUAD DUAL DUAL DUAL
width 4.4 mm 4.4 mm 3.9 mm 2.5 mm 2.5 mm 3.9 mm 4.4 mm 4.4 mm
Maker Nexperia - - - Nexperia Nexperia Nexperia Nexperia
Peak Reflow Temperature (Celsius) - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
What is the special purpose of inductors wound with silk wire?
This is the power supply I saw. There are two kinds of inductors in the power supply. One is an ordinary enameled wire inductor, and the other is wound with "silk wire". Does this kind of inductor hav...
bigbat Power technology
Domestic 51 single chip microcomputer
[i=s]This post was last edited by Northwest by Northwest1959 on 2022-7-18 16:27[/i]Domestic 51 single chip microcomputer TU8010CQF, suitable for atomizer, humidifier, power management, motor drive, wi...
西北偏北1959 51mcu
When using a transistor in the amplification area, which thermal resistance should be considered after considering the power?
When using a transistor in the amplification area, which thermal resistance should be considered after considering the power? How to choose? How much power can be used? The thermal resistance of the u...
小太阳yy Switching Power Supply Study Group
Design of breathing light based on FPGA
...
至芯科技FPGA大牛 FPGA/CPLD
TMS320C6678 device configuration pins and power-on timing
(1) LENDIAN: Determines the big and small endianness of the DSP.(2) BOOTMODE[12:0]: Determines the self-starting mode of the DSP (see BootLoader for the C66x DSP User Guide for details).(3) PCIESSMODE...
灞波儿奔 DSP and ARM Processors
Does anyone know what the diode in the picture does?
What are the functions of D2, D3, D4, D5, and D6 in the figure, and why are they connected like this?...
shijizai Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号