PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840-75
75MH
Z
, LVCMOS/LVTTL
O
SCILLATOR
R
EPLACEMENT
G
ENERAL
D
ESCRIPTION
The ICS840-75 is a SAS/SATA Oscillator
Replacement and a member of the
HiPerClockS™
HiPerClocks
TM
family of high perfor mance
devices from ICS. The ICS840-75 uses a
25MHz cr ystal to synthesize 75MHz. The
ICS840-75 has excellent jitter performance. The ICS840-75
is packaged in a small 8-pin TSSOP, making it ideal for
use in systems with limited board space.
F
EATURES
•
One LVCMOS/LVTTL output, 15Ω output impedence
•
Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
•
Output frequency: 75MHz
•
Random jitter: 3ps (typical)
•
Deterministic jitter: 0.14ps (typical)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
IC
S
B
LOCK
D
IAGRAM
OE
Pullup
P
IN
A
SSIGNMENT
V
DD
XTAL_OUT
XTAL_IN
OE
1
2
3
4
8
7
6
5
nc
Q
V
DDO
GND
25MHz
XTAL_IN
75MHz
Clock
Synthesizer
Q
ICS840-75
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
XTAL_OUT
ICS840-75
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
840AG-75
www.icst.com/products/hiperclocks.html
REV A. NOVEMBER 7, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840-75
75MH
Z
, LVCMOS/LVTTL
O
SCILLATOR
R
EPLACEMENT
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6
7
8
Name
V
DD
XTAL_OUT,
XTAL_IN
OE
GN D
V
DDO
Q
nc
Power
Input
Input
Power
Power
Output
Unused
Pullup
Type
Description
Power supply pin.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q output is enabled. When LOW,
forces Q output to HiZ state. LVCMOS/LVTTL interface levels.
Power supply ground.
Output supply pin.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15
Ω
output impedence.
No connect
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
51
15
Maximum
Units
pF
kΩ
Ω
T
ABLE
3. C
ONTROL
F
UNCTION
T
ABLE
Control Inputs
OE
0
1
Output
Q
Hi-Z
Active
840AG-75
www.icst.com/products/hiperclocks.html
2
REV A. NOVEMBER 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840-75
75MH
Z
, LVCMOS/LVTTL
O
SCILLATOR
R
EPLACEMENT
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
Package Thermal Impedance,
θ
JA
8 Lead TSSOP
101.7°C/W (0 mps)
8 Lead SOIC
Storage Temperature, T
STG
112.7°C/W (0 lfpm)
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
OE = V
DD
(output enabled)
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
80
8
Maximum
3.6
3.6
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
V
V
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
25
TBD
7
TBD
MHz
Ω
pF
µW
Maximum
Units
840AG-75
www.icst.com/products/hiperclocks.html
3
REV A. NOVEMBER 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840-75
75MH
Z
, LVCMOS/LVTTL
O
SCILLATOR
R
EPLACEMENT
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V,, T
A
= 0°C
TO
70°C
Symbol
f
OUT
t
DJ
t
RJ
t
RMS
t
p-p
t
acc
t
OSC
t
R
/ t
F
Parameter
Output Frequency
Deterministic Jitter ; NOTE 1
Random Jitter ; NOTE 1
RMS of Total Distribution (
σ
);
NOTE 1
Peak-to-Peak Jitter ; NOTE 1
Accumulated Jitter (
σ
);
NOTE 1
Oscillation Star t Up Time
Output Rise/Fall Time
Test Conditions
Minimum
Typical
75
0.14
3
3.05
2.7
n = 2 to 50000 cycles
Time at minimum operating voltage
to be 0 s
20% to 80%
TBD
50
TBD
10
Maximum
Units
MHz
ps
ps
ps
ps
ps
ms
ps
%
odc
Output Duty Cycle
NOTE 1: Measured using Wavecrest SIA-3000.
840AG-75
www.icst.com/products/hiperclocks.html
4
REV A. NOVEMBER 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840-75
75MH
Z
, LVCMOS/LVTTL
O
SCILLATOR
R
EPLACEMENT
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V ± 0.15V
V
DD,
V
DDO
SCOPE
Q
Qx
V
DDO
2
t
PW
t
PERIOD
LVCMOS
GND
odc =
-1.65V ± 0.15V
t
PW
t
PERIOD
x 100%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
80%
20%
t
R
80%
20%
t
F
Clock
Outputs
O
UTPUT
R
ISE
/F
ALL
T
IME
840AG-75
www.icst.com/products/hiperclocks.html
5
REV A. NOVEMBER 7, 2005
Power technology
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