IC41C1665
IC41LV1665
64K x 16 (1-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
•
•
•
•
•
•
DESCRIPTION
•
•
The
ICSI
IC41C1665 and the IC41LV1665 are 65,536 x 16-
Fast access and cycle time
bit high-performance CMOS Dynamic Random Access
TTL compatible inputs and outputs
Memory. Fast Page Mode allows 256 random accesses
Refresh Interval: 256 cycles/4 ms
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
Refresh Mode:
RAS-Only, CAS-before-RAS
byte, makes these devices ideal for use in 16-, 32-bit wide
(CBR), Hidden
data bus systems.
JEDEC standard pinout
These features make the IC41C1665 and the IC41LV1665
Single power supply:
ideally suited for high band-width graphics, digital signal
— 5V ± 10% (IC41C1665)
processing, high-performance computing systems, and
peripheral applications.
— 3.3V ± 10% (IC41LV1665)
The IC41C1665 and the IC41LV1665 are packaged in a 40-
Byte Write and Byte Read operation via
pin, 400mil SOJ and TSOP-2.
two
CAS
Available in 40-pin SOJ and TSOP-2
KEY TIMING PARAMETERS
Parameter
-25
-30
30
9
16
20
55
-35
35
10
18
23
65
-40
40
11
20
25
75
Unit
ns
ns
ns
ns
ns
Max.
RAS
Access Time (t
RAC
)
25
Max.
CAS
Access Time (t
CAC
)
8
Max. Column Address Access Time (t
AA
) 12
Min. Fast Page Mode Cycle Time (t
PC
)
15
PIN CONFIGURATIONS
40-Pin TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
Min. Read/Write Cycle Time (t
RC
)
43
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
NC
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A7
I/O0-I/O15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address
Strobe
Lower Column Address
Strobe
Power
Ground
No Connection
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
LCAS
UCAS
OE
NC
A7
A6
A5
A4
GND
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
IC41C1665
IC41LV1665
FUNCTIONAL DESCRIPTION
The IC41C1665 and the IC41LV1665 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
nine bits (A0-A7) at a time. The row address is latched by the
Row Address Strobe (RAS). The column address is latched
by the Column Address Strobe (CAS).
RAS
is used to latch
the first eight bits and
CAS
is used to latch the latter eight
bits.
The IC41C1665 and the IC41LV1665 have two
CAS
controls,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs internally
generate a
CAS
signal functioning in an identical manner to
the single
CAS
input on the other 64K x 16 DRAMs. The key
difference is that each
CAS
controls its corresponding I/O
tristate logic (in conjunction with
OE
and
WE
and
RAS).
LCAS
controls I/O0 - I/O7 and
UCAS
controls I/O8 - I/O15.
The IC41C1665/IC41LV1665
CAS
function is determined by
the first
CAS
(LCAS or
UCAS)
transitioning LOW and the last
transitioning back HIGH. The two
CAS
controls give the
IC41C1665 both BYTE READ and BYTE WRITE cycle
capabilities.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs last.
Refresh Cycle
To retain data, 256 refresh cycles are required in each
4 ms period. There are two ways to refresh the memory:
1. By clocking each of the 256 row addresses (A0 through
A7) with
RAS
at least once every 4 ms. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the ad-
dressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS
LOW. In
CAS-before-RAS
refresh cycle, an
internal 8-bit counter provides the row addresses and the
external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle must
not be initiated until the minimum precharge time t
RP
, t
CP
has
elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are
all satisfied. As a result, the access time is dependent on the
timing relationships between these parameters.
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
5
DigiKey Technology Zone
京公网安备 11010802033920号
EEWORLD
