Hitachi Single-Chip Microcomputer
H8S/2199 Series
H8S/2199
HD6432199
H8S/2198
HD6432198
H8S/2197
HD6432197
H8S/2196
HD6432196
H8S/2199F-ZTAT
HD64F2199
™
Hardware Manual
ADE-602-191
Rev 1.0
2/15/00
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Contents
Section 1
1.1
1.2
1.3
Overview
...........................................................................................................
Overview...........................................................................................................................
Internal Block Diagram.....................................................................................................
Pin Arrangement and Functions........................................................................................
1.3.1
Pin Arrangement...............................................................................................
1.3.2
Pin Functions ....................................................................................................
1
1
7
8
8
9
Section 2
2.1
CPU
.................................................................................................................... 17
17
17
18
18
19
20
25
26
26
27
28
29
30
30
32
33
33
34
35
45
46
47
47
50
54
54
55
56
57
58
59
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Overview...........................................................................................................................
2.1.1
Features.............................................................................................................
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU ...............................
2.1.3
Differences from H8/300 CPU .........................................................................
2.1.4
Differences from H8/300H CPU ......................................................................
CPU Operating Modes ......................................................................................................
Address Space...................................................................................................................
Register Configuration......................................................................................................
2.4.1
Overview ..........................................................................................................
2.4.2
General Registers..............................................................................................
2.4.3
Control Registers ..............................................................................................
2.4.4
Initial Register Values ......................................................................................
Data Formats.....................................................................................................................
2.5.1
General Register Data Formats.........................................................................
2.5.2
Memory Data Formats......................................................................................
Instruction Set ...................................................................................................................
2.6.1
Overview ..........................................................................................................
2.6.2
Instructions and Addressing Modes..................................................................
2.6.3
Table of Instructions Classified by Function ....................................................
2.6.4
Basic Instruction Formats .................................................................................
2.6.5
Notes on Use of Bit-Manipulation Instructions ................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1
Addressing Mode..............................................................................................
2.7.2
Effective Address Calculation ..........................................................................
Processing States...............................................................................................................
2.8.1
Overview ..........................................................................................................
2.8.2
Reset State ........................................................................................................
2.8.3
Exception-Handling State.................................................................................
2.8.4
Program Execution State ..................................................................................
2.8.5
Power-Down State ............................................................................................
Basic Timing.....................................................................................................................
Rev. 1.0, 02/00, page i of 19
2.9.1
2.9.2
2.9.3
Overview .......................................................................................................... 59
On-Chip Memory (ROM, RAM)...................................................................... 59
On-Chip Supporting Module Access Timing ................................................... 60
Section 3
3.1
MCU Operating Modes
................................................................................ 61
61
61
61
62
62
62
63
64
3.2
3.3
3.4
Overview...........................................................................................................................
3.1.1
Operating Mode Selection ................................................................................
3.1.2
Register Configuration......................................................................................
Register Descriptions ........................................................................................................
3.2.1
Mode Control Register (MDCR) ......................................................................
3.2.2
System Control Register (SYSCR)...................................................................
Operating Mode (Mode 1) ................................................................................................
Address Map in Each Operating Mode.............................................................................
Section 4
4.1
Power-Down State
......................................................................................... 67
67
71
72
72
74
76
77
78
79
79
79
80
80
81
81
81
81
83
83
83
84
84
84
85
85
85
86
86
Overview...........................................................................................................................
4.1.1
Register Configuration......................................................................................
4.2 Register Descriptions ........................................................................................................
4.2.1
Standby Control Register (SBYCR) .................................................................
4.2.2
Low-Power Control Register (LPWRCR) ........................................................
4.2.3
Timer Register A (TMA)..................................................................................
4.2.4
Module Stop Control Register (MSTPCR).......................................................
4.3 Medium-Speed Mode........................................................................................................
4.4 Sleep Mode .......................................................................................................................
4.4.1
Sleep Mode .......................................................................................................
4.4.2
Clearing Sleep Mode ........................................................................................
4.5 Module Stop Mode ...........................................................................................................
4.5.1
Module Stop Mode ...........................................................................................
4.6 Standby Mode ...................................................................................................................
4.6.1
Standby Mode...................................................................................................
4.6.2
Clearing Standby Mode ....................................................................................
4.6.3
Setting Oscillation Settling Time after Clearing Standby Mode ......................
4.7 Watch Mode......................................................................................................................
4.7.1
Watch Mode .....................................................................................................
4.7.2
Clearing Watch Mode.......................................................................................
4.8 Subsleep Mode..................................................................................................................
4.8.1
Subsleep Mode .................................................................................................
4.8.2
Clearing Subsleep Mode...................................................................................
4.9 Subactive Mode ................................................................................................................
4.9.1
Subactive Mode ................................................................................................
4.9.2
Clearing Subactive Mode .................................................................................
4.10 Direct Transition ...............................................................................................................
4.10.1
Overview of Direct Transition..........................................................................
Rev. 1.0, 02/00, page ii of 19
Section 5
5.1
Exception Handling
....................................................................................... 87
87
87
88
88
90
90
90
91
92
93
94
95
5.2
5.3
5.4
5.5
5.6
Overview...........................................................................................................................
5.1.1
Exception Handling Types and Priority............................................................
5.1.2
Exception Handling Operation .........................................................................
5.1.3
Exception Sources and Vector Table................................................................
Reset..................................................................................................................................
5.2.1
Overview ..........................................................................................................
5.2.2
Reset Sequence .................................................................................................
5.2.3
Interrupts after Reset.........................................................................................
Interrupts...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Use of the Stack .................................................................................................
Section 6 Interrupt Controller
.......................................................................................... 97
6.1
Overview...........................................................................................................................
6.1.1
Features.............................................................................................................
6.1.2
Block Diagram..................................................................................................
6.1.3
Pin Configuration .............................................................................................
6.1.4
Register Configuration......................................................................................
Register Descriptions ........................................................................................................
6.2.1
System Control Register (SYSCR)...................................................................
6.2.2
Interrupt Control Registers A to D (ICRA to ICRD)........................................
6.2.3
IRQ Enable Register (IENR) ............................................................................
6.2.4
IRQ Edge Select Registers (IEGR)...................................................................
6.2.5
IRQ Status Register (IRQR) .............................................................................
6.2.6
Port Mode Register (PMR1) .............................................................................
Interrupt Sources...............................................................................................................
6.3.1
External Interrupts ............................................................................................
6.3.2
Internal Interrupts .............................................................................................
6.3.3
Interrupt Exception Vector Table .....................................................................
Interrupt Operation............................................................................................................
6.4.1
Interrupt Control Modes and Interrupt Operation.............................................
6.4.2
Interrupt Control Mode 0..................................................................................
6.4.3
Interrupt Control Mode 1..................................................................................
6.4.4
Interrupt Exception Handling Sequence ...........................................................
6.4.5
Interrupt Response Times .................................................................................
Usage Notes ......................................................................................................................
6.5.1
Contention between Interrupt Generation and Disabling .................................
6.5.2
Instructions that Disable Interrupts...................................................................
6.5.3
Interrupts during Execution of EEPMOV Instruction ......................................
97
97
98
99
99
100
100
101
102
103
104
105
106
106
107
108
111
111
113
115
118
119
120
120
121
121
6.2
6.3
6.4
6.5
Rev. 1.0, 02/00, page iii of 19
Download Centre
京公网安备 11010802033920号
EEWORLD
