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AMD27C64-70JI

Description
64 Kilobit (8,192 x 8-Bit) CMOS EPROM
File Size74KB,11 Pages
ManufacturerAMD
Websitehttp://www.amd.com
Download Datasheet View All

AMD27C64-70JI Overview

64 Kilobit (8,192 x 8-Bit) CMOS EPROM

FINAL
Am27C64
64 Kilobit (8,192 x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s
Fast access time
45 ns
s
Low power consumption
20
µA
typical CMOS standby current
s
JEDEC-approved pinout
s
Single +5 V power supply
s
±10%
power supply tolerance available
s
100% Flashrite
TM
programming
— Typical programming time of 1 second
Advanced
Micro
Devices
s
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
s
High noise immunity
s
Versatile features for simple interfacing
— Both CMOS and TTL input/output
compatibility
— Two line control functions
s
Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C64 is a 64-Kbit ultraviolet erasable program-
mable read-only memory. It is organized as 8K words by
8 bits per word, operates from a single +5 V supply, has
a static standby mode, and features fast single address
location programming. Products are available in win-
dowed ceramic DIP packages as well as plastic one
time programmable (OTP) PDIP, and PLCC packages.
Typically, any byte can be accessed in less than 45 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C64 offers
separate Output Enable (OE) and Chip Enable (CE)
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100
µW
in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C64 supports AMD’s Flashrite
programming algorithm (100
µs
pulses) resulting in a
typical programming time of 1 second.
BLOCK DIAGRAM
V
CC
V
SS
V
PP
Data Outputs
DQ0–DQ7
OE
CE
PGM
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
Output
Buffers
Y
Gating
A0–A12
Address
Inputs
X
Decoder
65,538
Bit Cell
Matrix
11419D-1
2-10
Publication#
11419
Rev.
D
Issue Date:
May 1995
Amendment
/0
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