Cortina Systems
®
LXT973 10/100 Mbps
Dual-Port Fast Ethernet PHY Transceiver
Datasheet
The Cortina Systems
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
(LXT973 Transceiver) is an IEEE 802.3 compliant, dual-port, Fast Ethernet PHY
transceiver that directly supports both 100BASE-TX and 10BASE-T applications. Each
port provides a Media Independent Interface (MII) for easy attachment to 10 Mbps and
100 Mbps Media Access Controllers (MACs). The LXT973 Transceiver also provides a
Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface per port for use with
100BASE-FX fiber networks. The LXT973 Transceiver incorporates the auto MDI/MDIX
feature, allowing it to automatically switch twisted-pair inputs and outputs.
The LXT973 Transceiver is an ideal building block for systems that require two Ethernet
ports, such as Internet Protocol (IP) Telephones, Twisted-Pair (TX)-to-Fiber (FX)
converter modules, and for telecom applications, such as Telecom Central Office (TCO)
and Customer Premise Equipment (CPE) devices.
The LXT973 Transceiver supports full-duplex operation at both 10 Mbps and 100 Mbps.
Its operating modes can be set using auto-negotiation, parallel detection, or manual
control.
Applications
Enterprise switches
IP telephony switches
Storage Area Networks
Multi-port Network Interface Cards (NICs)
Product Features
Dual-port Fast Ethernet PHY
2.5 Voperation
3.3 Voperation I/O compatibility
Low power consumption; 250 mW per port
typical
Full dual-port MII interface with extended
registers
Auto MDI/MDIX switch over capability
Signal Quality Error (SQE) enable/disable
100BASE-FX fiber-optic capability on both ports
Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability
Support for Next Page
20 MHz Register Access
Configurable via MDIO port or external control
pins
Integrated termination resistors
100-pin Plastic Quad Flat Package (PQFP)
— Commercial (0
°
C to 70
°
C ambient)
SLXT973QC Transceiver
EGLXT973QC Transceiver (RoHS
Compliant)
— (-40
°
C to +85
°
C ambient) (Extended)
SLXT973QE Transceiver
EGLXT973QE Transceiver (RoHS
Compliant
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Legal Disclaimers
This document contains information proprietary to Cortina Systems, Inc. (Cortina). Any use or disclosure, in whole or in part, of this
information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as
authorized by Cortina in writing. Cortina reserves its rights to pursue both civil and criminal penalties for copying or disclosure of
this material without authorization.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS
®
PRODUCTS.
NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS
GRANTED BY THIS DOCUMENT.
EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES
NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE
SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear
facility applications.
Cortina Systems
®
and the Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its
subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others.
Copyright © 2001−2007 Cortina Systems, Inc. All rights reserved.
Cortina Systems
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Page 2
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Contents
Contents
1.0
2.0
3.0
Pin Assignments and Signal Descriptions ...............................................................................13
Signal Descriptions .....................................................................................................................17
Functional Description................................................................................................................23
3.1
3.2
3.3
Introduction .........................................................................................................................23
3.1.1 Comprehensive Functionality ................................................................................23
Interface Descriptions .........................................................................................................23
3.2.1 10/100 Mbps Network Interface .............................................................................23
MII Operation ......................................................................................................................25
3.3.1 MII Clocks ..............................................................................................................25
3.3.2 Transmit Enable.....................................................................................................25
3.3.3 Receive Data Valid ................................................................................................25
3.3.4 Carrier Sense.........................................................................................................26
3.3.5 Error Signals ..........................................................................................................26
3.3.6 Collision .................................................................................................................26
3.3.7 Loopback ...............................................................................................................26
3.3.8 Configuration Management Interface ....................................................................27
Operating Requirements.....................................................................................................29
3.4.1 Power Requirements .............................................................................................29
3.4.2 Clock Requirements ..............................................................................................30
Initialization .........................................................................................................................30
3.5.1 MDIO Control Mode ...............................................................................................30
3.5.2 Hardware Control Mode.........................................................................................30
3.5.3 Power-Down Mode ................................................................................................31
3.5.4 Reset .....................................................................................................................31
3.5.5 Hardware Configuration Settings ...........................................................................32
Link Establishment..............................................................................................................33
3.6.1 Auto-Negotiation ....................................................................................................33
Network Media/Protocol Support ........................................................................................34
3.7.1 10/100 Mbps Network Interface .............................................................................34
3.7.2 Twisted-Pair Interface ............................................................................................35
3.7.3 Fiber Interface........................................................................................................35
3.7.4 Fault Detection and Reporting ...............................................................................35
3.7.5 Remote Fault .........................................................................................................35
3.7.6 Far End Fault .........................................................................................................36
100 Mbps Operation ...........................................................................................................36
3.8.1 100BASE-X Network Operations ...........................................................................36
3.8.2 100BASE-X Protocol Sublayer Operations............................................................37
3.8.3 PCS Sublayer ........................................................................................................37
3.8.4 PMA Sublayer ........................................................................................................38
3.8.5 Fiber PMD Sublayer ..............................................................................................39
10 Mbps Operation .............................................................................................................40
3.9.1 Polarity Correction .................................................................................................40
3.9.2 Dribble Bits ............................................................................................................40
3.9.3 Link Test ................................................................................................................40
3.9.4 Link Failure ............................................................................................................40
3.9.5 Jabber ....................................................................................................................40
Monitoring Operations ........................................................................................................41
Page 3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Cortina Systems
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Contents
3.10.1 Monitoring Auto-Negotiation ..................................................................................41
3.10.2 Per-Port LED Driver Functions ..............................................................................41
4.0
Application Information ..............................................................................................................42
4.1
Design Recommendations..................................................................................................42
4.1.1 General Design Guidelines ....................................................................................42
4.1.2 Power Supply Filtering ...........................................................................................42
4.1.3 Power and Ground Plane Layout Considerations..................................................43
4.1.4 MII Terminations ....................................................................................................43
4.1.5 The Fiber Interface ................................................................................................44
4.1.6 Twisted-Pair Interface ............................................................................................45
4.1.7 Magnetics Information ...........................................................................................45
Typical Application Circuits .................................................................................................46
Initialization .........................................................................................................................51
MDIO Control Mode ............................................................................................................51
Manual Control Mode .........................................................................................................51
4.2
4.3
4.4
4.5
5.0
6.0
7.0
8.0
Configuration ...............................................................................................................................53
Auto Negotiation..........................................................................................................................55
Auto-MDI/MDIX.............................................................................................................................56
100 Mbps Operation ....................................................................................................................57
8.1
Displaying Symbol Errors ...................................................................................................57
8.1.1 Scrambler Seeding ................................................................................................58
8.1.2 Scrambler Bypass..................................................................................................58
8.1.3 100BASE-T Link Failure Criteria and Override ......................................................58
8.1.4 Baseline Wander Correction ..................................................................................58
8.1.5 Programmable Tx Slew Rate .................................................................................58
9.0
Fiber Interface ..............................................................................................................................60
10.0 10 Mbps Operation ......................................................................................................................61
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
11.1
Link Test .............................................................................................................................61
10Base-T Link Failure Criteria and Override ......................................................................61
SQE (Heartbeat) .................................................................................................................61
Jabber.................................................................................................................................61
Polarity Correction ..............................................................................................................61
Dribble Bits .........................................................................................................................62
Transmit Polarity Control ....................................................................................................62
PHY Address ......................................................................................................................62
External Oscillator...............................................................................................................63
11.0 Clock Generation.........................................................................................................................63
12.0 Register Definitions.....................................................................................................................65
13.0 Magnetics Information ................................................................................................................75
14.0 Test Specifications......................................................................................................................76
15.0 Timing Diagrams .........................................................................................................................81
Cortina Systems
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Page 4
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Contents
16.0 Mechanical Specifications ..........................................................................................................92
16.1
Top Label Marking ..............................................................................................................92
17.0 Product Ordering Information ....................................................................................................95
Cortina Systems
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Page 5
京公网安备 11010802033920号
EEWORLD
