XRD9855/9856
XRD98L55/98L56
CCD Image Digitizers with
CDS, PGA and 10-Bit A/D
July 2001
FEATURES
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10-Bit Resolution ADC
18 - 27MHz Maximum Sampling Rate
Correlated Double Sampling (CDS)
Programmable Gain from 6dB to 38dB (PGA)
Digitally Controlled Analog Offset-Calibration
CCD Black Level Offset Compensation at Frame
Rate
CDS Clocks Sample Rising Edge or Falling Edge
Single 5V or 3V Power Supply
Low Power for Battery Applications:
XRD9855/56:
XRD98L55/L56:
250/
300m W @ V
DD
= 5.0V
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3-State Digital Outputs
ESD Protection to Over 2000V
APPLICATIONS
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Digital Video Camcorders
Digital Still Cameras
PC Video Teleconferencing
Digital Copiers
Infrared Image Digitizers
CCD/CIS Imager Interface
CCTV/Security Camera
2D Bar Code Readers
Industrial Cameras
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120/150mW @ V
DD
= 3.0V
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50
µ
A-Typ Current in Stand By Mode
GENERAL DESCRIPTION
The XRD9855/XRD9856 are complete CCD Image
Digitizers for digital cameras. The products include a
high bandwidth differential Correlated Double Sampler
(CDS), 8-bit digitally Programmable Gain Amplifier
(PGA), 10-bit Analog-to-Digital Converter (ADC) and
digital controlled black level auto-calibration circuitry.
The C or el ed D oubl Sam pl ( D S ) subt act t
r at
e
er C
r s he
C C D out
put si
gnal bl
ack l
evel fom t vi
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he deo l
evel
.
C om m on m ode si
gnal se and pow ersuppl noi ar
noi
y se e
r ect by t dif ental D S i
ej ed
he fer i C
nputst
age.C D S i
nput
s
ar desi
e
gned t be used eiher dif entalor si e-
o
t
fer i
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ended.
The aut calbr i cicui com pensat f any i er
o
i aton r t
es or
nt -
nalofsetoft X R D 9855/ R D 9856 as w el as bl
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f
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he
The PGA is digitally controlled with 8-bit resolution on
a linear dB scale, resulting in a gain range of 6dB to
38dB with 0.125dB per LSB of the gain code.
The PGA and black level auto-calibration are controlled
through a simple 3-wire serial interface. The timing
circuitry is designed to enable users to select a wide
variety of available CCD and image sensors for their
applications.
The XRD9855/XRD9856 has direct access to the PGA
output and ADC input through the pin TESTVIN.
The XRD9855/XRD9856 are packaged in 48-lead sur-
face mount TQFP to reduce space and weight, and
suitable for hand-held and portable applications.
ORDERING INFORMATION
Part No.
XRD9855AIV
XRD98L55AIV
XRD9856AIV
XRD98L56AIV
Package
48 Lead TQFP (7 x 7 x 1.4 mm)
48 Lead TQFP (7 x 7 x 1.4 mm)
48 Lead TQFP (7 x 7 x 1.4 mm)
48 Lead TQFP (7 x 7 x 1.4 mm)
Operating
Temperature Range Power Supply
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
5.0V
3.0V
5.0V
3.0V
Maximum
Sampling Rate
18 MSPS
18 MSPS
27 MSPS
27 MSPS
Rev. 1.01
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRD9855/9856
XRD98L55/98L56
V
DD
GND
V
RBO
V
RB
TESTVIN
V
RT
V
RTO
V
DD
DV
DD
In_Pos
CDS
In_Neg
DGND
SHD
SHP
RSTCCD
CLAMP
CLK_POL
Timing
Generator
SYNC
OVER
Offset
Calibration
Serial Port
Registers
UNDER
PGA
ADC
Reg
DB[9:0]
SCLK
SDI
LOAD
GND
STBY1
STBY2
RESET
EnableCal
OE
Figure 1. XRD9855/XRD9856 Simplified Block Diagram
Rev. 1.01
2
XRD9855/9856
XRD98L55/98L56
NC
V
RB
V
RBO
GND
In_Pos
In_Neg
V
DD
V
RTO
V
RT
SDI
LOAD
NC
36
CLAMP
SHD
SHP
RSTCCD
GND
CLK_POL
V
DD
SYNC
UNDER
DB0
DB1
NC
37
25
24
PIN CONFIGURATION
48
1
12
13
SCLK
RESET
STBY2
STBY1
Test
GND
EnableCal
V
DD
OE
OVER
DB9
DB8
48 Lead TQFP (7 x 7 x 1.0 mm)
PIN DESCRIPTION – 48 pin TQFP
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol
NC
NC
DB2
DB3
DB4
DGND
DV
DD
DB5
DB6
DB7
NC
NC
DB8
DB9
OVER
Description
No Connect.
No Connect.
ADC Output.
DB0 is the LSB, DB9 is the MSB.
ADC Output.
ADC Output.
Digital Output Ground.
Digital Output Power Supply.
Must be less than or equal to V
DD
.
ADC Output.
ADC Output.
ADC Output.
No Connect.
No Connect.
ADC Output.
ADC Output.
MSB
Over Range Output Bit.
OVER goes high to indicate the ADC input voltage is
greater than V
RT
.
Rev. 1.01
3
NC
NC
DB2
DB3
DB4
DGND
DV
DD
DB5
DB6
DB7
NC
NC
XRD9855/9856
XRD98L55/98L56
PIN DESCRIPTION – 48 pin TQFP (CONT’D)
Pin #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
OE
V
DD
EnableCal
GND
TESTVIN
STBY1
STBY2
RESET
SCLK
NC
LOAD
SDI
V
RT
V
RTO
V
DD
In_Neg
In_Pos
GND
V
RBO
V
RB
NC
CLAMP
SHD
SHP
RSTCCD
GND
CLK_POL
V
DD
SYNC
UNDER
DBO
DB1
NC
Description
Digital Output Enable (Three-State Control).
Pull OE low to enable output
drivers. Pull OE high to put output drivers in high impedance state.
Analog Power Supply.
Calibration Enable.
Automatic offset calibration control.
Analog Ground.
ADC Test Input & PGA Test Output.
Standby Control 1.
Pull low to put chip in power down mode.
Standby Control 2.
Short to STBY1 pin if not using TESTVIN pin.
Chip Reset.
Pull high to reset all internal registers.
Shift Clock.
Shift register latches SDI data on rising edges of SCLK.
No Connect.
Data Load.
Rising edge loads data from shift register to internal register. Load
must be low to enable shift register.
Serial Data Input.
Top ADC Reference.
Voltage at V
RT
sets full-scale of ADC.
Internal Bias for V
RT
.
Short V
RT
to V
RTO
to use internal reference voltage.
Analog Power Supply.
CDS Inverting Input.
Connect via capacitor to CCD video output.
CDS Non-inverting Input.
Connect via capacitor to CCD supply.
Analog Ground.
Internal Bias for V
RB.
Short V
RB
to V
RB0
to use internal reference voltage.
Bottom ADC Reference.
Voltage at V
RB
sets zero scale of the ADC.
No Connect.
CDS DC Restore Clamp.
Clamps In_Pos & In_Neg to internal bias voltage.
CDS Clock.
Controls sampling of the pixel video level.
CDS Clock.
Controls sampling of the pixel black level.
CCD Reset Pulse Disconnect.
Used to decouple CDS during the reset pulse.
Analog Ground.
Clock Polarity.
Controls the polarity of SHP, SHD & CLAMP.
Analog Power Supply.
Digital output for Exar test purposes only.
No connect.
Under Range Output Bit.
UNDER goes high to indicate the ADC input voltage
is less than V
RB
.
ADC Output.
LSB
ADC Output.
No Connect.
Rev. 1.01
4
XRD9855/9856
XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS – XRD9855 and XRD9856
Unl
ess ot
herw i speci i
se
f ed: D V
DD
= V
DD
= 5.0V, Pixel Rate = 18MSPS, V
RT
= 3.8V, V
RB
= 0.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
CDS Performance
CDSV
IN
BW
SR
FT
Input Range
Small Signal Bandwidth (-3dB)
Slew Rate
Feed–through (Hold Mode)
200
60
40
-60
800
mV
PP
MHz
V/µs
dB
400mV Step Input
Pixel (Black Level - Video Level)
PGA Parameters
AV
MIN
AV
MAX
PGA n
GE
Minimum Gain
Maximum Gain
Resolution
Gain Error
3.5
35.5
5
37
8
5
6.5
38.5
dB
dB
bits
% FS
Transfer function is linear steps in dB
(1LSB = 0.125dB)
At maximum or minimum gain
setting
ADC Parameters (Measured Through TESTVIN)
ADC n
f
s
DNL
Resolution
Max Sample Rate
Differential Non-Linearity
10
27
-1
+0.75
1.2
bits
MSPS
LSB
Up to 18MHz sample rate
(XRD9855)
DNL27
Differential Non-Linearity
-1
+1.3
2.0
LSB
Up to 27MHz sample rate
(XRD9856)
EZS
EFS
V
IN
Zero Scale Error
Full Scale Error
DC Input Range
GND
-50
50
4
V
DD
mV
% FS
V
V
IN
of the ADC can swing from GND
to V
DD
. Input range is limited by
the output swing of the PGA
V
RT
>V
RB
V
RT
>V
RB
Measured relative to V
RB
V
RT
V
RB
∆V
REF
R
L
V
RB
V
RT
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
Ladder Resistance
1.5
0.3
1.0
280
3.8
0.5
3.3
400
V
DD
V
DD
-1
V
DD
520
V
V
V
Ohms
Self Bias V
RB
Self Bias V
RT
(
(
V
RB
= V
DD
10
V
RT
= V
DD
1.30
)
)
0.4
0.5
0.6
V
V
RB
connected to V
RBO
V
RT
connected to V
RTO
3.5
3.8
4.1
V
Rev. 1.01
5
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