M5M54R16ATP-12 datasheet, PDF - EEWORLD Datasheet

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M5M54R16ATP-12: Description4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM; Categorystorage storage; File Size54KB，7 Pages; ManufacturerMitsubishi; Websitehttp://www.mitsubishielectric.com/semiconductors/

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M5M54R16ATP-12 Overview

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

M5M54R16ATP-12 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Mitsubishi
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP44,.46,32
Contacts	44
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	12 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G44
JESD-609 code	e0
length	18.41 mm
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	16
Number of functions	1
Number of terminals	44
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP44,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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1998.11.30 Ver.B

MITSUBISHI LSIs

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

M5M54R16AJ,ATP-10,-12,-15

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

DESCRIPTION

The M5M54R16A is a family of 262144-word by 16-bit

static RAMs, fabricated with the high performance CMOS

process and designed for high speed application. These

devices operate on a single 3.3V supply, and are directly

TTL compatible.

They include a power down feature as well. In write

and read cycles, the lower and upper bytes are able

to be controled either togethe or separately by LB

and UB.

CHIP SELECT

INPUT

DATA

INPUTS/

OUTPUTS

ADDRESS

INPUTS

PIN CONFIGURATION (TOP VIEW)

FEATURES

•Fast access time

M5M54R16AJ,ATP-10 ... 10ns(max)

M5M54R16AJ,ATP-12 ... 12ns(max)

M5M54R16AJ,ATP-15 ... 15ns(max)

(3.3V)

(0V)

ADDRESS

INPUTS

OUTPUT

ENABLE INPUT

BYTE

CONTROL

INPUTS

15 DATA

INPUTS/

14 OUTPUTS

GND

(0V)

•Single +3.3V power supply

•Fully static operation : No clocks, No refresh

•Common data I/O

•Easy memory expansion by S

•Three-state outputs : OR-tie capability

•OE prevents data contention in the I/O bus

•Directly TTL compatible : All inputs and outputs

•Separate control of lower and upper bytes by LB and UB

GND

DATA

INPUTS/

OUTPUTS

WRITE

CONTROL INPUT

ADDRESS

INPUTS

N.C

(3.3V)

DATA

INPUTS/

OUTPUTS

ADDRESS

INPUTS

Outline

44P0K

APPLICATION

High-speed memory system

PACKAGE

M5M54R16AJ .......... 44pin 400mil SOJ

M5M54R16ATP .......... 44pin 400mil TSOP(II)

state. (LB and/or UB=L, S=L)

When setting LB at a high level and other pins are in

an active state, upper-Byte are in a selectable mode

in which both reading and writing are enable, and

lower-Byte are in a non-selectable mode. And when

setting UB at a high level and other pins are in an

active state, lower-Byte are in a selectable mode in

which both reading and writing are enable, and upper-

Byte are in a non-selectable mode.

When setting LB and UB at a high level or S at high

level, the chip is in a non-selectable mode in which

both reading and writing are disabled. In this mode,

the output stage is in a high-impedance state,

allowing OR-tie with other chips and memory

expansion by LB, UB and S.

Signal-S controls the power-down feature. When S

goes high, power dissapation is reduced extremely.

The access time from S is equivalent to the address

access time.

FUNCTION

The operation mode of the M5M54R16A is determined

by a combination of the device control inputs S, W, OE,

LB, and UB. Each mode is summarized in the function

table.

A write cycle is executed whenever the low level W

overlaps with low level LB and/or low level UB and low

level S. The address must be set-up before write cycle

and must be stable during the entire cycle.

The data is latched into a cell on the traling edge of

W, LB, UB or S, whichever occurs first, requiring the

set-up and hold time relative to these edge to be

maintained. The output enable input OE directly

controls the output stage. Setting the OE at a high level,

the output stage is in a high impedance state, and the

data bus contention problem in the write cycle is

eliminated.

A read cycle is excuted by setting W at a high level

and OE at a low level while LB and/or UB and S are in

an active

MITSUBISHI

ELECTRIC

M5M54R16ATP-12 Related Products

	M5M54R16ATP-12	M5M54R16ATP-15	M5M54R16AJ-15	M5M54R16ATP-10	M5M54R16AJ-10	M5M54R16AJ-12
Description	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Mitsubishi	Mitsubishi	Mitsubishi	Mitsubishi	Mitsubishi	Mitsubishi
Parts packaging code	TSOP2	TSOP2	SOJ	TSOP2	SOJ	SOJ
package instruction	TSOP2, TSOP44,.46,32	TSOP2, TSOP44,.46,32	SOJ, SOJ44,.44	TSOP2, TSOP44,.46,32	SOJ, SOJ44,.44	SOJ, SOJ44,.44
Contacts	44	44	44	44	44	44
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	12 ns	15 ns	15 ns	10 ns	10 ns	12 ns
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PDSO-G44	R-PDSO-G44	R-PDSO-J44	R-PDSO-G44	R-PDSO-J44	R-PDSO-J44
JESD-609 code	e0	e0	e0	e0	e0	e0
length	18.41 mm	18.41 mm	28.57 mm	18.41 mm	28.57 mm	28.57 mm
memory density	4194304 bi	4194304 bi	4194304 bi	4194304 bi	4194304 bi	4194304 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1
Number of terminals	44	44	44	44	44	44
word count	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000	256000	256000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	256KX16	256KX16	256KX16	256KX16	256KX16	256KX16
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	SOJ	TSOP2	SOJ	SOJ
Encapsulate equivalent code	TSOP44,.46,32	TSOP44,.46,32	SOJ44,.44	TSOP44,.46,32	SOJ44,.44	SOJ44,.44
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	3.55 mm	1.2 mm	3.55 mm	3.55 mm
Maximum standby current	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.25 mA	0.23 mA	0.23 mA	0.26 mA	0.26 mA	0.25 mA
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	J BEND	GULL WING	J BEND	J BEND
Terminal pitch	0.8 mm	0.8 mm	1.27 mm	0.8 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Maximum supply voltage (Vsup)	3.6 V	-	-	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	-	-	3 V	3 V	3 V

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