74VHC74MTCX_NL datasheet, PDF - EEWORLD Datasheet

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74VHC74MTCX_NL: DescriptionAHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14; Categorylogic logic; File Size104KB，8 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14

74VHC74MTCX_NL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP14,.25
Contacts	14
Reach Compliance Code	compli
series	AHC/VHC/H/U/V
JESD-30 code	R-PDSO-G14
JESD-609 code	e3
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Su	75000000 Hz
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of digits	1
Number of functions	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	2/5.5 V
Prop。Delay @ Nom-Su	10.5 ns
propagation delay (tpd)	17.5 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	4.4 mm
minfmax	110 MHz
Base Number Matches	1

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74VHC74 Dual D-Type Flip-Flop with Preset and Clear

October 1992

Revised February 2005

74VHC74

Dual D-Type Flip-Flop with Preset and Clear

General Description

The VHC74 is an advanced high speed CMOS Dual D-

Type Flip-Flop fabricated with silicon gate CMOS technol-

ogy. It achieves the high speed operation similar to equiva-

lent Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The signal level applied to the D input is

transferred to the Q output during the positive going transi-

tion of the CK pulse. CLR and PR are independent of the

CK and are accomplished by setting the appropriate input

LOW.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery backup. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

High Speed: f

MAX

170 MHz (typ) at T

NIL

High noise immunity: V

NIH

Low power dissipation: I

28% V

(min)

Power down protection is provided on all inputs

A (max) at T

Pin and function compatible with 74HC74

Ordering Code:

Order Number

74VHC74M

74VHC74MX_NL

74VHC74SJ

74VHC74MTC

74VHC74MTCX_NL

(Note 1)

74VHC74N

Package

Number

M14A

M14D

MTC14

N14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDED J-STD-020B.

Note 1:

“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

DS011505

www.fairchildsemi.com

74VHC74MTCX_NL Related Products

	74VHC74MTCX_NL	74VHC74MX_NL	74VHC74	74VHC74MTC	74VHC74N	74VHC74SJ
Description	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
series	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V
Number of digits	1	1	1	1	1	1
Number of functions	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 Cel	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 Cel	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
surface mount	YES	YES	Yes	YES	NO	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	GULL WING
Terminal location	DUAL	DUAL	pair	DUAL	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE edge	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
Is it Rohs certified?	conform to	conform to	-	conform to	conform to	conform to
Maker	Fairchild	Fairchild	-	Fairchild	Fairchild	Fairchild
Parts packaging code	TSSOP	SOIC	-	TSSOP	DIP	SOP
package instruction	TSSOP, TSSOP14,.25	SOP, SOP14,.25	-	TSSOP, TSSOP14,.25	DIP, SOP14,.25	SOP, SOP14,.3
Contacts	14	14	-	14	14	14
Reach Compliance Code	compli	compli	-	compli	compli	compli
JESD-30 code	R-PDSO-G14	R-PDSO-G14	-	R-PDSO-G14	R-PDIP-T14	R-PDSO-G14
JESD-609 code	e3	e3	-	e4	e3	e3
length	5 mm	8.625 mm	-	5 mm	19.18 mm	10.2 mm
Load capacitance (CL)	50 pF	50 pF	-	50 pF	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	-	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Su	75000000 Hz	75000000 Hz	-	75000000 Hz	75000000 Hz	75000000 Hz
MaximumI(ol)	0.008 A	0.008 A	-	0.008 A	0.008 A	0.008 A
Humidity sensitivity level	1	1	-	1	-	1
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP	-	TSSOP	DIP	SOP
Encapsulate equivalent code	TSSOP14,.25	SOP14,.25	-	TSSOP14,.25	SOP14,.25	SOP14,.3
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE	SMALL OUTLINE
method of packing	TAPE AND REEL	TAPE AND REEL	-	RAIL	RAIL	RAIL
Peak Reflow Temperature (Celsius)	260	260	-	NOT SPECIFIED	NOT APPLICABLE	260
power supply	2/5.5 V	2/5.5 V	-	2/5.5 V	2/5.5 V	2/5.5 V
Prop。Delay @ Nom-Su	10.5 ns	10.5 ns	-	10.5 ns	10.5 ns	10.5 ns
propagation delay (tpd)	17.5 ns	17.5 ns	-	17.5 ns	17.5 ns	17.5 ns
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.75 mm	-	1.2 mm	5.33 mm	2.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	-	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	-	2 V	2 V	2 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V
technology	CMOS	CMOS	-	CMOS	CMOS	CMOS
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal pitch	0.65 mm	1.27 mm	-	0.65 mm	2.54 mm	1.27 mm
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT APPLICABLE	NOT SPECIFIED
width	4.4 mm	3.9 mm	-	4.4 mm	7.62 mm	5.3 mm
minfmax	110 MHz	110 MHz	-	110 MHz	110 MHz	110 MHz
Base Number Matches	1	1	-	1	-	1

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