H8/3068 F-ZTAT™
HD64F3068
Hardware Manual
ADE-602-244
Rev. 1.0
3/22/01
Hitachi, Ltd.
Cautions
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have received the latest product standards or specifications before final design, purchase or
use.
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However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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semiconductor products.
Preface
The H8/3068F is a series of high-performance single-chip microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a DMA controller (DMAC), and
other facilities. The three-channel SCI has been expanded to support the ISO/IEC7816-3 smart
card interface. Functions have also been added to reduce power consumption in battery-powered
applications: individual modules can be placed in standby, and the frequency of the system clock
supplied to the chip can be divided down under software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3068F offers easy implementation of compact, high-performance
systems.
The H8/3068F has an F-ZTAT™* version with on-chip flash memory that can be programmed
on-board. This version enables users to respond quickly and flexibly to changing application
specifications.
This manual describes the H8/3068F hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ (Flexible ZTAT) is a registered trademark of Hitachi, Ltd.
Contents
Section 1
1.1
1.2
1.3
Overview..........................................................................................
1
1
6
7
7
8
Overview............................................................................................................................
Block Diagram ...................................................................................................................
Pin Description...................................................................................................................
1.3.1 Pin Arrangement ...................................................................................................
1.3.2 Pin Functions ........................................................................................................
Section 2
2.1
CPU.................................................................................................. 19
19
19
20
21
21
22
22
23
24
25
26
26
28
29
29
30
31
40
41
43
43
45
49
49
50
50
52
53
53
53
54
i
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Overview............................................................................................................................
2.1.1 Features .................................................................................................................
2.1.2 Differences from H8/300 CPU .............................................................................
CPU Operating Modes .......................................................................................................
Address Space....................................................................................................................
Register Configuration .......................................................................................................
2.4.1 Overview...............................................................................................................
2.4.2 General Registers..................................................................................................
2.4.3 Control Registers ..................................................................................................
2.4.4 Initial CPU Register Values..................................................................................
Data Formats......................................................................................................................
2.5.1 General Register Data Formats.............................................................................
2.5.2 Memory Data Formats..........................................................................................
Instruction Set ....................................................................................................................
2.6.1 Instruction Set Overview ......................................................................................
2.6.2 Instructions and Addressing Modes......................................................................
2.6.3 Tables of Instructions Classified by Function ......................................................
2.6.4 Basic Instruction Formats .....................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions ....................................................
Addressing Modes and Effective Address Calculation......................................................
2.7.1 Addressing Modes ................................................................................................
2.7.2 Effective Address Calculation ..............................................................................
Processing States................................................................................................................
2.8.1 Overview...............................................................................................................
2.8.2 Program Execution State ......................................................................................
2.8.3 Exception-Handling State .....................................................................................
2.8.4 Exception-Handling Sequences ............................................................................
2.8.5 Bus-Released State................................................................................................
2.8.6 Reset State ............................................................................................................
2.8.7 Power-Down State ................................................................................................
Basic Operational Timing ..................................................................................................
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