NE80546PG0881M datasheet, PDF - EEWORLD Datasheet

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NE80546PG0881M: DescriptionMicroprocessor, 32-Bit, 3200MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，81 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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NE80546PG0881M Overview

Microprocessor, 32-Bit, 3200MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478

NE80546PG0881M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
Parts packaging code	PGA
package instruction	SPGA,
Contacts	478
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	200 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P478
length	35 mm
low power mode	YES
Number of terminals	478
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
Certification status	Not Qualified
Maximum seat height	4.5 mm
speed	3200 MHz
Maximum supply voltage	1.4 V
Minimum supply voltage	1.25 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Intel

Pentium

4 Processor on

90 nm Process

Datasheet

2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading

Technology

for All Frequencies with 800 MHz Front Side Bus

February 2005

Document Number: 300561-003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

Pentium

4 processor on 90 nm process may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Hyper-Threading Technology requires a computer system with an Intel

Pentium

4 processor supporting HT Technology and a Hyper-Threading

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use.

See

http://www.intel.com/info/hyperthreading/

for more information including details on which processors support HT Technology.

Intel, Pentium, Intel NetBurst, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States

and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

Introduction

.................................................................................................................. 9

1.1

1.2

Terminology......................................................................................................... 10

1.1.1 Processor Packaging Terminology......................................................... 10

References .......................................................................................................... 11

Power and Ground Pins ...................................................................................... 13

Decoupling Guidelines ........................................................................................ 13

2.2.1 V

Decoupling ...................................................................................... 13

2.2.2 FSB GTL+ Decoupling ........................................................................... 13

2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking.................................... 14

Voltage Identification ........................................................................................... 14

2.3.1 Phase Lock Loop (PLL) Power and Filter............................................... 16

Reserved, Unused, and TESTHI Pins.................................................................17

FSB Signal Groups..............................................................................................18

Asynchronous GTL+ Signals............................................................................... 19

Test Access Port (TAP) Connection.................................................................... 19

FSB Frequency Select Signals (BSEL[1:0]) ........................................................ 20

Absolute Maximum and Minimum Ratings .......................................................... 21

Processor DC Specifications............................................................................... 21

Overshoot Specification............................................................................... 29

2.11.1 Die Voltage Validation ............................................................................ 30

Package Mechanical Specifications .................................................................... 31

3.1.1 Package Mechanical Drawing ................................................................ 32

3.1.2 Processor Component Keep-out Zones ................................................. 35

3.1.3 Package Loading Specifications ............................................................ 35

3.1.4 Package Handling Guidelines ................................................................ 35

3.1.5 Package Insertion Specifications ........................................................... 36

3.1.6 Processor Mass Specification ................................................................ 36

3.1.7 Processor Materials................................................................................ 36

3.1.8 Processor Markings................................................................................ 36

3.1.9 Processor Pinout Coordinates................................................................ 37

Processor Pin Assignments ................................................................................ 39

Alphabetical Signals Reference .......................................................................... 54

Processor Thermal Specifications....................................................................... 63

5.1.1 Thermal Specifications ........................................................................... 63

5.1.2 Thermal Metrology ................................................................................. 66

Processor Thermal Features............................................................................... 67

5.2.1 Thermal Monitor ..................................................................................... 67

Electrical Specifications

........................................................................................ 13

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

Package Mechanical Specifications

.................................................................31

3.1

Pin List and Signal Description

.......................................................................... 39

4.1

4.2

Thermal Specifications and Design Considerations

................................. 63

5.1

5.2

Datasheet

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

On-Demand Mode.................................................................................. 68

PROCHOT# Signal Pin .......................................................................... 68

THERMTRIP# Signal Pin ....................................................................... 69

control

and Fan Speed Reduction.......................................................... 69

Thermal Diode........................................................................................ 69

Features

....................................................................................................................... 71

6.1

6.2

Power-On Configuration Options ........................................................................ 71

Clock Control and Low Power States.................................................................. 72

6.2.1 Normal State—State 1 ........................................................................... 72

6.2.2 AutoHALT Powerdown State—State 2 .................................................. 72

6.2.3 Stop-Grant State—State 3 ..................................................................... 73

6.2.4 HALT/Grant Snoop State—State 4 ........................................................ 73

6.2.5 Sleep State—State 5.............................................................................. 74

Mechanical Specifications ................................................................................... 76

7.1.1 Boxed Processor Cooling Solution Dimensions ..................................... 76

7.1.2 Boxed Processor Fan Heatsink Weight.................................................. 77

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach

Clip Assembly ........................................................................................ 78

Electrical Requirements ...................................................................................... 78

7.2.1 Fan Heatsink Power Supply ................................................................... 78

Thermal Specifications........................................................................................ 79

7.3.1 Boxed Processor Cooling Requirements ............................................... 79

7.3.2 Variable Speed Fan ............................................................................... 81

Boxed Processor Specifications

....................................................................... 75

7.1

7.2

7.3

Datasheet

Figures

Phase Lock Loop (PLL) Filter Requirements ...................................................... 16

Static and Transient Tolerance for Loadline A............................................. 24

Static and Transient Tolerance for Loadline B............................................. 26

Overshoot Example Waveform.................................................................... 30

Processor Package Assembly............................................................................. 31

Processor Package Drawing (Sheet 1 of 2) ........................................................ 33

Processor Package Drawing (Sheet 2 of 2) ........................................................ 34

Processor Top-Side Markings ............................................................................. 36

Processor Pinout Coordinates (Top View) .......................................................... 37

Pinout Diagram (Top View—Left Side) ............................................................... 40

Pinout Diagram (Top View—Right Side) ............................................................. 41

Thermal Profile .................................................................................................... 66

Case Temperature (TC) Measurement Location................................................. 66

Stop Clock State Machine ................................................................................... 72

Mechanical Representation of the Boxed Processor .......................................... 75

Space Requirements for the Boxed Processor (Side View)................................ 76

Space Requirements for the Boxed Processor (Top View)................................. 77

Boxed Processor Fan Heatsink Power Cable Connector Description................. 78

Baseboard Power Header Placement Relative to Processor Socket.................. 79

Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(side 1 view) ........................................................................................................ 80

Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(side 2 view) ........................................................................................................ 80

Boxed Processor Fan Heatsink Set Points ......................................................... 81

Datasheet

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Description	Microprocessor, 32-Bit, 3200MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 3200MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 3200MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 3000MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478	Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA478, 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478
Maker	Intel	Intel	Intel	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA
package instruction	SPGA,	SPGA, BGA478,26X26,50	SPGA,	SPGA,	SPGA, BGA478,26X26,50	SPGA,	SPGA,	SPGA,	SPGA, BGA478,26X26,50
Contacts	478	478	478	478	478	478	478	478	478
Reach Compliance Code	compliant	unknown	compliant	unknown	compliant	compliant	compliant	compliant	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	36	36	36	36	36	36	36	36	36
bit size	32	32	32	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	200 MHz	200 MHz	200 MHz	133 MHz	200 MHz	200 MHz	133 MHz	200 MHz	133 MHz
External data bus width	64	64	64	64	64	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478
length	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	478	478	478	478	478	478	478	478	478
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.5 mm	4.5 mm	4.5 mm	4.5 mm	4.5 mm	4.5 mm	4.5 mm	4.5 mm	4.5 mm
speed	3200 MHz	2800 MHz	3200 MHz	2800 MHz	3200 MHz	3000 MHz	2800 MHz	2800 MHz	2800 MHz
Maximum supply voltage	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V
Minimum supply voltage	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Base Number Matches	1	1	1	1	1	1	1	1	1
Is it Rohs certified?	conform to	conform to	-	conform to	conform to	-	-	-	conform to

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