EEWORLDEEWORLDEEWORLD

Part Number

Search

ICS9248YF-112

Description
Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size385KB,12 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

ICS9248YF-112 Overview

Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48

ICS9248YF-112 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP,
Contacts48
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresIT CAN ALSO OPERATES AT 3.3V
JESD-30 codeR-PDSO-G48
JESD-609 codee0
length15.875 mm
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency150 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
Master clock/crystal nominal frequency14.318 MHz
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.5 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS9248-112
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Output Features:
2- CPUs @2.5V, up to 150MHz.
9 - SDRAM @ 3.3V, up to150MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz
2 - 3V66MHz @ 3.3V, 2X PCI MHz
1- 48MHz, @3.3V fixed.
1- 24MHz, @3.3V fixed
1- REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support FS0-FS3 strapping status bit for I
2
C read back.
Support power management: Through Power down
Mode from I
2
C programming.
Spread spectrum for EMI control ( ± 0.25% center).
Spread can be enabled or disabled to all 32 frequencies
throuth I
2
C.
Uses external 14.318MHz crystal
Skew Specifications:
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship.
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
1 These are double strength.
Block Diagram
Functionality
FS3 FS2 FS1 FS0
CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz)
PCICLK
(MHz)
I OA P I C
1=PCICLK/2
I OA P I C
0=PCICLK
(MHz)
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.80
68.00
100.30
103.00
133.73
145.00
133.73
137.33
140.00
140.00
118.00
124.00
133.70
137.00
150.00
72.50
100.20
102.00
100.30
103.00
100.30
108.75
100.30
103.00
105.00
140.00
118.00
124.00
133.70
137.00
112.50
108.75
66.80
68.00
66.87
68.67
66.87
72.50
66.87
68.67
70.00
93.33
78.67
82.67
89.13
91.33
75.00
72.50
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
Additional frequencies selectable through I
2
C programming.
9248- 112 Rev A 2/7/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

ICS9248YF-112 Related Products

ICS9248YF-112 ICS9248YF-112LF
Description Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48 Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48
Is it lead-free? Contains lead Lead free
Is it Rohs certified? incompatible conform to
Parts packaging code SSOP SSOP
package instruction SSOP, SSOP,
Contacts 48 48
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Other features IT CAN ALSO OPERATES AT 3.3V IT CAN ALSO OPERATES AT 3.3V
JESD-30 code R-PDSO-G48 R-PDSO-G48
JESD-609 code e0 e3
length 15.875 mm 15.875 mm
Number of terminals 48 48
Maximum operating temperature 70 °C 70 °C
Maximum output clock frequency 150 MHz 150 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 225 260
Master clock/crystal nominal frequency 14.318 MHz 14.318 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 2.794 mm 2.794 mm
Maximum supply voltage 2.625 V 2.625 V
Minimum supply voltage 2.375 V 2.375 V
Nominal supply voltage 2.5 V 2.5 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 7.5 mm 7.5 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches 1 1
What is the principle behind this?
Why does the gyroscope data change significantly when high voltage is close to the LSM6DSOX, but the acceleration does not?...
littleshrimp MEMS sensors
Sell yourself, sell yourself
Although it is posted here, the title is no joke. I've recently been trying to embark on the path of freelancing.I can write code, boards, and soft manuscripts. If you need anything, please find me~~~...
辛昕 Talking
ICE40LP1K CDONE pin is always low
The following code resets ICE40LP1K, but it is found that the CDONE pin is always at a low level and will not be pulled high. Is there any other initialization operation?uint32_t fpga_reset(){fpga_ini...
jplzl10000 FPGA/CPLD
Is there a company where you can have breakfast until 10 o'clock, take a nap until 2 o'clock, and receive 18 months' salary per year?
A netizen answered a post about the daily schedule of a tech company.A Taiwanese netizen said that his daily routine used to be as follows:09:00 Arrive at the company and swipe your card09:20 Eat brea...
赵玉田 Talking
[Automatic clock-in and walking timing system based on face recognition] Maixbit/MaixPy pitfall! The audio playback function blocks the call
Problem: The audio file is blocked from playing in a loop, and the screen cannot refresh the image captured by the camera in real time (there is a "stuck picture"). Try to use the state machine to pla...
alanlan86 DigiKey Technology Zone
1
[i=s] This post was last edited by qq825117996 on 2020-9-3 11:12[/i]void MX_TIM7_Init(void) {LL_TIM_InitTypeDef TIM_InitStruct = {0};/* Peripheral clock enable */LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_...
qq825117996 stm32/stm8

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号