ISPGAL22V10AV-5LJI datasheet, PDF

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ISPGAL22V10AV-5LJI: DescriptionSPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD; CategoryProgrammable logic devices Programmable logic; File Size523KB，20 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ISPGAL22V10AV-5LJI Overview

SPLD - Simple Programmable Logic Devices PROGRAMMABLE LO VOLT E2CMOS PLD

ISPGAL22V10AV-5LJI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QLCC
package instruction	PLASTIC, LCC-28
Contacts	28
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
Architecture	PAL-TYPE
maximum clock frequency	143 MHz
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.5062 mm
Humidity sensitivity level	1
Dedicated input times	11
Number of I/O lines	10
Number of entries	22
Output times	10
Number of product terms	132
Number of terminals	28
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Programmable logic type	EE PLD
propagation delay	5 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	11.5062 mm
Base Number Matches	1

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ispGAL™22V10AV/B/C Device Datasheet

June 2010

All Devices Discontinued!

Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in

this data sheet.

The original datasheet pages have not been modified and do not reflect those changes.

Please refer to the table below for reference PCN and current product status.

Product Line

ispGAL22V10AV

ispGAL22V10AB

Ordering Part Number

ispGAL22V10AV-23LS

ispGAL22V10AV-23LSN

ispGAL22V10AV-5LS

ispGAL22V10AV-5LSN

ispGAL22V10AV-75LS

ispGAL22V10AV-75LSN

ispGAL22V10AV-5LSI

ispGAL22V10AV-5LSNI

ispGAL22V10AV-75LSI

ispGAL22V10AV-75LSNI

ispGAL22V10AV-28LJ

ispGAL22V10AV-5LJ

ispGAL22V10AV-75LJ

ispGAL22V10AV-5LJI

ispGAL22V10AV-75LJI

ispGAL22V10AB-23LS

ispGAL22V10AB-5LS

ispGAL22V10AB-75LS

ispGAL22V10AB-5LSI

ispGAL22V10AB-75LSI

ispGAL22V10AB-28LJ

ispGAL22V10AB-5LJ

ispGAL22V10AB-75LJ

ispGAL22V10AB-5LJI

ispGAL22V10AB-75LJI

Product Status

Reference PCN

Discontinued

PCN#09-10

Discontinued

PCN#09-10

5555 N.E. Moore Ct.

Hillsboro, Oregon 97124-6421 Phone (503) 268-8000

Internet: http://www.latticesemi.com

FAX (503) 268-8347

Lattice Semiconductor

ispGAL22V10AV/B/C Data Sheet

ispGAL Architecture

Output Logic Macrocell (OLMC)

The ispGAL22V10A has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs

have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve

product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen

product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional

product-term dedicated to output enable control.

The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or

registered mode. This allows each output to be individually conﬁgured as either active high or active low.

D LL

C DE

TI CE

Figure 2. Output Logic Macrocell

The ispGAL22V10A has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset

(SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to

zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on

the rising edge of the next clock pulse after this product term is asserted.

NOTE: The AR and SP product terms will force the Q output of the ﬂip-ﬂop into the same state regardless of the

polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a

high or low at the output pin, depending on the pin polarity chosen.

4 TO 1

MUX

CLK

2 TO 1

MUX

Output Logic Macrocell Conﬁgurations

Each of the Macrocells of the ispGAL22V10A has two primary functional modes: registered, and combinatorial I/O.

The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic com-

piler. Each of these two primary modes, and the bit settings required to enable them, are described below and on

the following page.

Registered

In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-

type ﬂip-ﬂop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive

either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for

each OLMC, and can therefore be deﬁned by a logic equation. The D ﬂip-ﬂop’s /Q output is fed back into the AND

array, with both the true and complement of the feedback available as inputs to the AND array.

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Reach Compliance Code	not_compliant	not_compliant	not_compliant	compliant	not_compliant	unknown	not_compliant	unknown	unknown	unknown
Number of terminals	28	32	32	2	32	32	32	32	28	32
Package form	CHIP CARRIER	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Axial	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
technology	CMOS	CMOS	CMOS	METAL FILM	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Is it Rohs certified?	incompatible	incompatible	incompatible	-	incompatible	conform to	incompatible	conform to	incompatible	conform to
Maker	Lattice	Lattice	Lattice	-	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice
Parts packaging code	QLCC	QFN	QFN	-	QFN	QFN	QFN	QFN	QLCC	QFN
package instruction	PLASTIC, LCC-28	5 X 5 MM, QFN-32	QFN-32	-	QFN-32	5 X 5 MM, LEAD FREE, QFN-32	QFN-32	5 X 5 MM, LEAD FREE, QFN-32	PLASTIC, LCC-28	5 X 5 MM, LEAD FREE, QFN-32
Contacts	28	32	32	-	32	32	32	32	28	32
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	-	EAR99	EAR99	EAR99
Architecture	PAL-TYPE	PAL-TYPE	PAL-TYPE	-	PAL-TYPE	-	PAL-TYPE	-	PAL-TYPE	-
maximum clock frequency	143 MHz	100 MHz	303 MHz	-	100 MHz	143 MHz	143 MHz	100 MHz	143 MHz	143 MHz
JESD-30 code	S-PQCC-J28	S-XQCC-N32	S-XQCC-N32	-	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32	S-PQCC-J28	S-XQCC-N32
JESD-609 code	e0	e0	e0	-	e0	e3	e0	e3	e0	e3
length	11.5062 mm	5 mm	5 mm	-	5 mm	5 mm	5 mm	5 mm	11.5062 mm	5 mm
Humidity sensitivity level	1	1	1	-	1	1	1	1	1	1
Dedicated input times	11	11	11	-	11	11	11	11	11	11
Number of I/O lines	10	10	10	-	10	10	10	10	10	10
Number of entries	22	22	22	-	22	-	22	-	22	-
Output times	10	10	10	-	10	-	10	-	10	-
Number of product terms	132	132	132	-	132	-	132	-	132	-
organize	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	-	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	UNSPECIFIED	UNSPECIFIED	-	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	PLASTIC/EPOXY	UNSPECIFIED
encapsulated code	QCCJ	HVQCCN	HVQCCN	-	HVQCCN	HVQCCN	HVQCCN	HVQCCN	QCCJ	HVQCCN
Encapsulate equivalent code	LDCC28,.5SQ	LCC32(UNSPEC)	LCC32(UNSPEC)	-	LCC32(UNSPEC)	-	LCC32(UNSPEC)	-	LDCC28,.5SQ	-
Package shape	SQUARE	SQUARE	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Peak Reflow Temperature (Celsius)	225	240	240	-	240	260	240	260	225	260
power supply	3.3 V	1.8 V	3.3 V	-	3.3 V	-	2.5 V	-	2.5 V	-
Programmable logic type	EE PLD	EE PLD	EE PLD	-	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	5 ns	7.5 ns	2.3 ns	-	7.5 ns	5 ns	5 ns	7.5 ns	5 ns	5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	1 mm	1 mm	-	1 mm	1 mm	1 mm	1 mm	4.57 mm	1 mm
Maximum supply voltage	3.6 V	1.95 V	3.6 V	-	3.6 V	3.6 V	2.7 V	3.6 V	2.7 V	3.6 V
Minimum supply voltage	3 V	1.65 V	3 V	-	3 V	3 V	2.3 V	3 V	2.3 V	3 V
Nominal supply voltage	3.3 V	1.8 V	3.3 V	-	3.3 V	3.3 V	2.5 V	3.3 V	2.5 V	3.3 V
surface mount	YES	YES	YES	-	YES	YES	YES	YES	YES	YES
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	-	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)
Terminal form	J BEND	NO LEAD	NO LEAD	-	NO LEAD	NO LEAD	NO LEAD	NO LEAD	J BEND	NO LEAD
Terminal pitch	1.27 mm	0.5 mm	0.5 mm	-	0.5 mm	0.5 mm	0.5 mm	0.5 mm	1.27 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	-	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	-	30	40	30	40	30	40
width	11.5062 mm	5 mm	5 mm	-	5 mm	5 mm	5 mm	5 mm	11.5062 mm	5 mm

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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