MCM6209CJ35 datasheet, PDF - EEWORLD Datasheet

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MCM6209CJ35: Description64K x 4 Bit Fast Static RAM; Categorystorage storage; File Size89KB，8 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM6209CJ35 Overview

64K x 4 Bit Fast Static RAM

MCM6209CJ35 Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	SOJ
package instruction	SOJ,
Contacts	28
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	35 ns
I/O type	COMMON
JESD-30 code	R-PDSO-J28
JESD-609 code	e0
length	18.415 mm
memory density	262144 bi
Memory IC Type	STANDARD SRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	28
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX4
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	SOJ
Encapsulate equivalent code	SOJ28,.34
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.75 mm
Maximum standby current	0.02 A
Minimum standby current	4.5 V
Maximum slew rate	0.13 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.62 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM6209C/D

64K x 4 Bit Fast Static RAM

With Output Enable

The MCM6209C is fabricated using Motorola’s high–performance silicon–gate

CMOS technology. Static design eliminates the need for external clocks or timing

strobes, while CMOS circuitry reduces power consumption and provides for

greater reliability.

This device meets JEDEC standards for functionality and pinout, and is avail-

able in plastic dual–in–line and plastic small–outline J–leaded packages.

Single 5 V

10% Power Supply

Fully Static — No Clock or Timing Strobes Necessary

Fast Access Times: 12, 15, 20, 25, and 35 ns

Equal Address and Chip Enable Access Times

Output Enable (G) Feature for Increased System Flexibility and to

Eliminate Bus Contention Problems

•

Low Power Operation: 135 – 165 mA Maximum AC

•

Fully TTL Compatible — Three–State Output

•

MCM6209C

P PACKAGE

300 MIL PLASTIC

CASE 710B–01

J PACKAGE

300 MIL SOJ

CASE 810B–03

PIN ASSIGNMENT

VCC

A15

A14

A13

A12

A11

A10

DQ0

DQ1

DQ2

DQ3

BLOCK DIAGRAM

A12

A13

A14

ROW

DECODER

MEMORY ARRAY

256 ROWS x

64 x 4 COLUMNS

VCC

VSS

DQ0

DQ1

DQ2

DQ3

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

VSS

PIN NAMES

A10 A11 A15

A0 – A15 . . . . . . . . . . . . . Address Input

DQ0 – DQ3 . . . Data Input/Data Output

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

NC . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . Power Supply (+ 5 V)

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

REV 3

5/95

Motorola, Inc. 1995

MOTOROLA FAST SRAM

MCM6209C

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