IMPORTANT NOTICE
Dear customer,
As from August 2
nd
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - NXP B.V.
is replaced with
ST-NXP Wireless.
Copyright
- the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site
-
http://www.nxp.com
is replaced with
http://www.stnwireless.com
Contact information
- the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
, is now found at
http://www.stnwireless.com
under Contacts.
●
●
●
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
www.stnwireless.com
ISP1583
Hi-Speed USB peripheral controller
Rev. 07 — 22 September 2008
Product data sheet
1. General description
The ISP1583 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus
(USB) peripheral controller. It fully complies with
Ref. 1 “Universal Serial Bus Specification
Rev. 2.0”,
supporting data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s).
The ISP1583 provides high-speed USB communication capacity to systems based on
microcontrollers or microprocessors. It communicates with a microcontroller or
microprocessor of a system through a high-speed general-purpose parallel interface.
The ISP1583 supports automatic detection of Hi-Speed USB system operation. Original
USB fall-back mode allows the device to remain operational under full-speed conditions. It
is designed as a generic USB peripheral controller so that it can fit into all existing device
classes, such as imaging class, mass storage devices, communication devices, printing
devices and human interface devices.
The ISP1583 is a low-voltage device, which supports I/O pad voltages from 1.65 V to
3.6 V.
The internal generic Direct Memory Access (DMA) block allows easy integration into data
streaming applications. In addition, the various configurations of the DMA block are
tailored for mass storage applications.
The modular approach to implementing a USB peripheral controller allows the designer to
select the optimum system microcontroller from the wide variety available. The ability to
reuse existing architecture and firmware shortens the development time, eliminates risk
and reduces cost. The result is fast and efficient development of the most cost-effective
USB peripheral solution.
The ISP1583 also incorporates features such as SoftConnect, a reduced frequency
crystal oscillator and integrated termination resistors. These features allow significant cost
savings in system design and easy implementation of advanced USB functionality into PC
peripherals.
2. Features
I
Complies fully with:
N
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
N
Most device class specifications
N
ACPI, OnNow and USB power management requirements
I
Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)
I
Direct interface to ATA/ATAPI peripherals; applicable only in split bus mode
I
High performance USB peripheral controller with integrated Serial Interface Engine
(SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Automatic Hi-Speed USB mode detection and Original USB fall-back mode
Supports sharing mode
Supports I/O voltage range of 1.65 V to 3.6 V
Supports V
BUS
sensing
High-speed DMA interface
Configurable direct access data path from the microprocessor to an ATA device
Fully autonomous and multiconfiguration DMA operation
Seven IN endpoints, seven OUT endpoints, and a fixed control IN and OUT endpoint
Integrated physical 8 kB of multiconfiguration FIFO memory
Endpoints with double buffering to increase throughput and ease real-time data
transfer
Bus-independent interface with most microcontrollers and microprocessors
12 MHz crystal oscillator with integrated PLL for low EMI
Software-controlled connection to the USB bus (SoftConnect)
Low-power consumption in operation and power-down modes; suitable for use in
bus-powered USB devices
Supports Session Request Protocol (SRP) that adheres to
Ref. 2 “On-The-Go
Supplement to the USB Specification Rev. 1.3”
Internal power-on and low-voltage reset circuits; also supports software reset
Operation over the extended USB bus voltage range (DP, DM and V
BUS
)
5 V tolerant I/O pads
Operating temperature range from
−40 °C
to +85
°C
Available in HVQFN64 and TFBGA64 halogen-free and lead-free packages
3. Applications
I
I
I
I
I
I
I
I
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Personal digital assistant
Mass storage device, for example: CD, DVD, Magneto-Optical (MO) and Zip drives
Digital video camera
Digital still camera
3G mobile phone
MP3 player
Communication device, for example: router and modem
Printer
Scanner
ISP1583_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
2 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
4. Ordering information
Table 1.
Ordering information
Package
Name
ISP1583BS
ISP1583ET
ISP1583ET1
[1]
ISP1583ET2
[1]
[1]
Type number
Description
Version
HVQFN64
TFBGA64
TFBGA64
TFBGA64
plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-1
body 9
×
9
×
0.85 mm
plastic thin fine-pitch ball grid array package; 64 balls; body 6
×
6
×
0.8 mm
plastic thin fine-pitch ball grid array package; 64 balls; body 4
×
4
×
0.8 mm
plastic thin fine-pitch ball grid array package; 64 balls; body 6
×
6
×
0.8 mm
SOT543-1
SOT969-1
SOT543-1
Contains solder ball material SAC105.
5. Marking
Table 2.
Marking codes
Marking code
[1]
ISP1583BS
ISP1583
1583
1583ET2
Type number
ISP1583BS
ISP1583ET
ISP1583ET1
ISP1583ET2
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1583_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
3 of 99
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Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
ISP1583_7
6. Block diagram
NXP Semiconductors
to or from USB
DP DM
12 MHz
V
BUS
XTAL1 XTAL2
CS1_N DA1
(2)
DREQ
CS0_N DA0
(3)
DA2
DIOR
DACK DIOW
10 11 12
8
EOT
INTRQ
IORDY
(1)
3
3.3 V
1.5 kΩ
4
55
58
57
21 22 62 60 17 9
ISP1583
SoftConnect
DMA
HANDLER
DMA INTERFACE
14
15
RPU
2
37 to 40,
42 to 53
DMA
REGISTERS
62
60
34
MICRO-
CONTROLLER
HANDLER
MICROCONTROLLER
INTERFACE
SYSTEM
CONTROLLER
I/O pad supply
13, 35, 59
1, 5
32, 56
64
63
26, 41, 54
V
CC(I/O)
004aaa268
16
RREF
12 kΩ
6
HI-SPEED USB
TRANSCEIVER
NXP
SIE/PIE
MEMORY
MANAGEMENT
UNIT
DATA[15:0]
BUS_CONF
(3)
MODE0
(2)
MODE1
8
RESET_N
7
POWER-ON
RESET
internal
reset
analog
supply
23 to 25,
27 to 31
18
36
19
20
INTEGRATED
RAM (8 kB)
AD[7:0]
CS_N
ALE/A0
RW_N/RD_N
DS_N/WR_N
READY
(1)
INT
V
CC(3V3)
61
VOLTAGE
1.8 V digital
REGULATORS
supply
OTG SRP
MODULE
15
16
Hi-Speed USB peripheral controller
DGND AGND VCC1V8
SUSPEND WAKEUP
The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see
Table 3.
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register).
(1) Pin 15 is shared by READY and IORDY.
(2) Pin 60 is shared by MODE0 and DA1.
(3) Pin 62 is shared by BUS_CONF and DA0.
ISP1583
4 of 99
Fig 1.
Block diagram
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