CY7C1049D-10VXIT datasheet, PDF

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CY7C1049D-10VXIT: DescriptionLVDS Interface IC 3.125GBPS LVDS BFR; Categorystorage; File Size389KB，15 Pages; ManufacturerCypress Semiconductor

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CY7C1049D-10VXIT Overview

LVDS Interface IC 3.125GBPS LVDS BFR

CY7C1049D-10VXIT Parametric

Parameter Name	Attribute value
Product Category	SRAM
Manufacturer	Cypress Semiconductor
RoHS	Details
Memory Size	4 Mbit
Organization	512 k x 8
Access Time	10 ns
Maximum Clock Frequency	100 MHz
Interface Type	Parallel
Supply Voltage - Max	5.5 V
Supply Voltage - Min	4.5 V
Supply Current - Max	90 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	SOJ-36
Packaging	Reel
Packaging	MouseReel
Packaging	Cut Tape
Memory Type	SDR
Moisture Sensitive	Yes
Factory Pack Quantity	500
Type	Asynchronous

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CY7C1049D

4-Mbit (512 K × 8) Static RAM

Features

■

Pin- and function-compatible with CY7C1049B

High speed

❐

= 10 ns

Low active power

❐

= 90 mA at 10 ns

Low CMOS Standby power

❐

SB2

= 10 mA

2.0 V data retention

Automatic power-down when deselected

TTL-compatible inputs and outputs

Easy memory expansion with CE and OE features

Available in Pb-free 36-pin (400-Mil) Molded SOJ package

provided by an active LOW Chip Enable (CE), an active LOW

Output Enable (OE), and tri-state drivers. Writing to the device is

accomplished by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O

through I/O

)

is then written into the location specified on the address pins (A

through A

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O

through I/O

) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), or during a write operation

(CE LOW, and WE LOW).

The CY7C1049D is available in a standard 400-mil-wide 36-pin

SOJ package with center power and ground (revolutionary)

pinout.

The CY7C1049D is suitable for interfacing with processors that

have TTL I/P levels. It is not suitable for processors that require

CMOS I/P levels. Please see

Electrical Characteristics on page

for more details and suggested alternatives.

For a complete list of related documentation,

click here.

■

Functional Description

The CY7C1049D

[1]

is a high-performance CMOS static RAM

organized as 512K words by 8 bits. Easy memory expansion is

Logic Block Diagram

I/O

INPUT BUFFER

I/O

ROW DECODER

I/O

SENSE AMPS

512K x 8

I/O

COLUMN

DECODER

POWER

DOWN

I/O

Note

1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at

www.cypress.com.

Cypress Semiconductor Corporation

Document Number: 38-05474 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 24, 2014

CY7C1049D-10VXIT Related Products

	CY7C1049D-10VXIT
Description	LVDS Interface IC 3.125GBPS LVDS BFR
Product Category	SRAM
Manufacturer	Cypress Semiconductor
RoHS	Details
Memory Size	4 Mbit
Organization	512 k x 8
Access Time	10 ns
Maximum Clock Frequency	100 MHz
Interface Type	Parallel
Supply Voltage - Max	5.5 V
Supply Voltage - Min	4.5 V
Supply Current - Max	90 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	SOJ-36
Packaging	Cut Tape
Memory Type	SDR
Moisture Sensitive	Yes
Factory Pack Quantity	500
Type	Asynchronous

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