SY58607U
3.2Gbps Precision, 1:2 LVPECL Fanout
Buffer with Internal Termination and Fail
Safe Input
General Description
The SY58607U is a 2.5/3.3V, high-speed, fully
differential 1:2 LVPECL fanout buffer optimized to
provide two identical output copies with less than 20ps
of skew and less than 10ps
pp
total jitter. The SY58607U
can process clock signals as fast as 2.5GHz or data
patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mV
pp
) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (V
REF-AC
) is provided to bias the V
T
pin.
The outputs are 800mV LVPECL, with extremely fast
rise/fall times guaranteed to be less than 110ps.
The SY58607U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range (–40°C to +85°C). For
applications that require CML or LVDS outputs, consider
the SY58606U and SY58608U, 1:2 fanout buffers with
400mV and 325mV output swings respectively. The
SY58607U is part of Micrel’s high-speed, Precision
®
Edge
product line.
Datasheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Features
Precision Edge
®
•
Precision 1:2, 800mV LVPECL fanout buffer
•
Guaranteed AC performance over temperature and
voltage:
–
DC-to > 3.2Gbps throughput
–
<350ps propagation delay (IN-to-Q)
–
<20ps within-device skew
–
<110ps rise/fall times
•
Fail Safe Input
–
Prevents outputs from oscillating when input is
invalid
•
Ultra-low jitter design
–
85fs RMS phase jitter
•
High-speed LVPECL outputs
•
2.5V ±5% or 3.3V ±10% power supply operation
•
Industrial temperature range:
–40°C
to +85°C
•
Available in 16-pin (3mm x 3mm) QFN package
Applications
•
•
•
•
All SONET clock and data distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Backplane distribution
Functional Block Diagram
Markets
•
•
•
•
•
•
•
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Oct. 1, 2013
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58607U
Ordering Information
(1)
Part Number
SY58607UMG
SY58607UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
(2)
Package
Type
QFN-16
QFN-16
Operating
Range
Industrial
Industrial
Package Marking
607U with Pb-Free
bar-line
indicator
607U with Pb-Free
bar-line
indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
1, 4
Pin Name
IN, /IN
Pin Function
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mVpp). Each pin
of
this pair internally terminates with 50Ω to the VT pin. If the input swing falls below
a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the output to its last valid state. See “Input Interface
Applications” subsection.
Input Termination Center-Tap: Each input terminates to this pin. The V
T
pin
provides a center-tap for each input (IN, /IN) to a termination network for maximum
interface flexibility. See “Input Interface Applications” subsection.
Reference Voltage: This output biases to V
CC
–1.2V.
It is used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass
with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA.
See “Input Interface Applications” subsection.
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the V
CC
pins as possible.
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
LVPECL Differential Output Pairs: Differential buffered copies of the input signal.
The output swing is typically 800mV. Unused output pair may be left floating with
no impact on jitter. See “LVPECL Output Termination” subsection.
2
VT
4
VREF-AC
5, 8,13, 16
6, 7, 14, 15
9, 10
11, 12
VCC
GND,
Exposed pad
/Q1, Q1
/Q0, Q0
Oct. 1, 2013
2
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58607U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
)
............................... –0.5V
to +4.0V
Input Voltage (V
IN
)
....................................... –0.5V
to V
CC
LVPECL Output Current(I
OUT
)
Continuous
.......................................................
50mA
Surge
.............................................................
100mA
Current (V
T
)
Source or sink on VT pin
.............................
±100mA
Input Current
Source or sink Current on (IN, /IN)
................
±50mA
Current (V
REF
)
(4)
Source or sink current on V
REF-AC
..............
±1.5mA
Maximum operating Junction Temperature
..........
125°C
Lead Temperature (soldering, 20sec.)
..................
260°C
Storage Temperature (T
s
)
.................... –65°C
to +150°C
Operating Ratings
(2)
Supply Voltage (V
IN
)
........................
+2.375V to +3.60V
Ambient Temperature (T
A
)
................... –40°C
to +85°C
(3)
Package Thermal Resistance
QFN
Still-air (θ
JA
)
............................................
60°C/W
Junction-to-board (ψ
JB
)
.........................
33°C/W
DC Electrical Characteristics
(5)
T
A
=
–40°C
to +85°C, unless otherwise
stated.
Symbol
V
CC
I
CC
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
IN_FSI
V
REF-AC
IN to V
T
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum
ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
ψ
JB
and
θ
JA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IN
(max) is specified when V
T
is floating.
7. V
IH
(min) not lower than 1.2V.
Parameter
Power Supply Voltage Range
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
(|IN
-
/IN|)
Input Voltage Threshold that
Triggers FSI
Output Reference Voltage
Condition
Min
2.375
3.0
Typ
2.5
3.3
40
Max
2.625
3.6
60
110
V
CC
V
IH
–0.1
1.7
Units
V
mA
Ω
V
V
V
V
No load, max. V
CC
90
IN, /IN, Note 7
IN, /IN
see Figure 3a, Note 6
see Figure 3b
V
CC
–1.6
0
0.1
0.2
100
30
V
CC
–1.3
V
CC
–1.2
100
V
CC
–1.1
1.28
mV
V
V
Oct. 1, 2013
3
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58607U
LVPECL Outputs DC Electrical Characteristics
(7)
V
CC
= +2.5V ±5% or +3.3V ±10%, R
L
= 50Ω to V
CC
-2V;
T
A
=
–40°C
to +85°C, unless otherwise stated.
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Notes:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
Differential Output Voltage Swing
Condition
Q0, /Q0, Q1, /Q1
Q0, /Q0, Q1, /Q1
See Figure 3a
See Figure 3b
Min
V
CC
-1.145
V
CC
-1.945
550
1100
Typ
Max
V
CC
-0.895
V
CC
-1.695
Units
V
V
mV
mV
800
1600
950
Oct. 1, 2013
4
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58607U
AC Electrical Characteristics
V
CC
= +2.5V ±5% or +3.3V ±10%, R
L
= 50Ω to V
CC
-2V,
Input t
r
/t
f
:
<300ps;
T
A
=
–40°C
to +85°C, unless otherwise
stated.
Symbol
f
MAX
t
PD
t
Skew
t
Jitter
t
r,
t
f
Parameter
Maximum Frequency
Propagation Delay
Within Device Skew
Part-to-Part
Skew
RMS Phase Jitter
Output Rise/Fall Time
(20% to 80%)
Duty Cycle
Notes:
8.
9.
Within device skew is measured between two different outputs under identical input transitions.
Part-to-part
skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Condition
NRZ Data
V
OUT
> 400mV
IN-to-Q
V
IN
: 100mV-200mV
V
IN
: 200mV-800mV
Note 8
Note 9
Output = 622MHz
Integration Range 12kHz
–
20MHz
At full output swing.
Differential I/O
Clock
Min
3.2
2.5
180
150
Typ
4.25
3
300
230
4
85
Max
Units
Gbps
GHz
450
350
20
135
ps
ps
ps
ps
fs
40
47
75
110
53
ps
%
Oct. 1, 2013
5
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
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