ATF1502ASV-15JI44 datasheet, PDF

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ATF1502ASV-15JI44: DescriptionCPLD - Complex Programmable Logic Devices CPLD 32 MACROCELL ISP STD PWR 3.3V; CategoryProgrammable logic devices Programmable logic; File Size254KB，26 Pages; ManufacturerAtmel (Microchip)

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ATF1502ASV-15JI44 Overview

CPLD - Complex Programmable Logic Devices CPLD 32 MACROCELL ISP STD PWR 3.3V

ATF1502ASV-15JI44 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	LPCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	unknown
Other features	YES
maximum clock frequency	100 MHz
In-system programmable	YES
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
JTAG BST	YES
length	16.5862 mm
Humidity sensitivity level	2
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	3 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm

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Features

•

High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 3.0 to 3.6V Operating Range

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 Pins

– 15 ns Maximum Pin-to-pin Delay

– Registered Operation up to 77 MHz

– Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

Advanced Power Management Features

– Pin-controlled 0.75 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-lead PLCC and TQFP

Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

Security Fuse Feature

Green (Pb/Halide-fee/RoHS Compliant) Package Options

•

High-

performance

EEPROM CPLD

ATF1502ASV

•

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D Latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Power-up Reset Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– Individual Macrocell Power Option

1615J–PLD–01/06

ATF1502ASV

1.3

Flip-flop

The ATF1502ASV’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin. Select-

ing the separate product term allows creation of a buried registered feedback within a

combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-

ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-

through latch. In this mode, data passes through when the clock is high and is latched when the

clock is low.

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual product

term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the

clock, one of the macrocell product terms can be selected as a clock enable. When the clock

enable function is active and the enable signal (product term) is low, all clock edges are ignored.

The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a prod-

uct term, or always off. AR can also be a logic OR of GCLEAR with a product term. The

asynchronous preset (AP) can be a product term or always off.

1.4

Extra Feedback

The ATF1502ASV macrocell output can be selected as registered or combinatorial.The extra

buried feedback signal can be either combinatorial or a registered signal regardless of whether

the output is combinatorial or registered. (This enhancement function is automatically imple-

mented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a

second latch within a macrocell.

1.5

I/O Control

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individ-

ually configured as an input, output or for bi-directional operation. The output enable for each

macrocell can be selected from the true or compliment of the two output enable pins, a subset of

the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter

software when the I/O is configured as an input, all macrocell resources are still available,

including the buried feedback, expander and cascade logic.

1.6

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from

all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the

global bus. Under software control, up to 40 of these signals can be selected as inputs to the

logic block.

1.7

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus and

is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s prod-

uct terms. The four foldback terms in each region allow generation of high fan-in sum terms (up

to nine product terms) with little additional delay.

2. Programmable Pin-keeper Option for Inputs and I/Os

The ATF1502ASV offers the option of programming all input and I/O pins so that pin-keeper cir-

cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will

stay at that previous high or low level. This circuitry prevents unused input and I/O lines from

1615J–PLD–01/06

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