MC100LVEL38
3.3V ECL
÷2, ÷4/6
Clock
Generation Chip
The MC100LVEL38 is a low skew
÷2, ÷4/6
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either a
differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as can happen with an
asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the
÷2
and the
÷4/6
outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the
÷2
and the
÷4/6
outputs of a
single device.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
Description
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SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL38
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
•
•
•
•
•
•
50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
•
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
−3.0
V to
−3.8
V
•
Internal Input 75 kW Pulldown Resistors
•
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
•
Moisture Sensitivity Pb = Level 1
Pb−Free = Level 3
For Additional Information, see Application Note
AND8003/D
•
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
•
Transistor Count = 388 devices
•
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2008
November, 2008
−
Rev. 10
1
Publication Order Number:
MC100LVEL38/D
MC100LVEL38
V
CC
20
Q0
19
Q0
18
Q1
17
Q1
16
Q2
15
Q2
14
Q3
13
Q3
12
V
EE
11
1
V
CC
2
3
4
5
CLK
6
V
BB
7
MR
8
9
10
EN DIV_SEL CLK
V
CC
Phase_Out Phase_Out
Figure 1. Pinout: 20-Lead SOIC
(Top View)
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Q0
CLK
CLK
÷2
R
Q0
Q1
Q1
EN
Q2
R
÷4/6
R
Q2
Q3
Q3
MR
DIVSEL
Phase
Out
Logic
R
PHASE_OUT
PHASE_OUT
V
BB
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
CLK, CLK
Q
0
, Q
1;
Q
0
, Q
1
Q
2
, Q
3;
Q
2
, Q
3
EN
MR
DIVSEL
Phase_Out, Phase_Out
V
BB
V
CC
V
EE
Function
ECL Diff Clock Inputs
ECL Diff
÷2
Outputs
ECL Diff
÷4/6
Outputs
ECL Sync Enable Input
ECL Master Reset Input
ECL Frequency Select Input
ECL Phase Sync Diff. Signal Output
Reference Voltage Output
Positive Supply
Negative Supply
Table 2. FUNCTION TABLE
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
Function
Divide
Hold Q
0−3
Reset Q
0−3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
X = Don’t Care
DVSEL
L
H
Q
2
, Q
3
OUTPUTS
Divide by 4
Divide by 6
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2
MC100LVEL38
CLK
Q (÷2)
Q (÷4)
Q (÷6)
Phase_Out (÷4)
Phase_Out (÷6)
Figure 3. Timing Diagrams
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
SOIC−20
SOIC−20
SOIC−20
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
±
0.5
−40
to +85
−65
to +150
90
60
30 to 35
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC100LVEL38
Table 4. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
Input HIGH Current
Input LOW Current
0.5
2215
1470
2135
1490
1.92
1.65
Min
Typ
50
2295
1605
Max
60
2420
1745
2420
1825
2.04
2.75
150
0.5
2275
1490
2135
1490
1.92
1.65
Min
25°C
Typ
50
2345
1595
Max
60
2420
1680
2420
1825
2.04
2.75
150
0.5
2275
1490
2135
1490
1.92
1.65
Min
85°C
Typ
54
2345
1595
Max
65
2420
1680
2420
1825
2.04
2.75
150
Unit
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP Min
and 1.0 V.
Table 5. LVNECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 4)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
Input HIGH Current
Input LOW Current
0.5
−1085
−1830
−1165
−1810
−1.38
−1.65
Min
Typ
50
−1005
−1695
Max
60
−880
−1555
−880
−1475
−1.26
−0.55
150
0.5
−1025
−1810
−1165
−1810
−1.38
−1.65
Min
25°C
Typ
50
−955
−1705
Max
60
−880
−1620
−880
−1475
−1.26
−0.55
150
0.5
−1025
−1810
−1165
−1810
−1.38
−1.65
Min
85°C
Typ
54
−955
−1705
Max
65
−880
−1620
−880
−1475
−1.26
−0.55
150
Unit
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
5. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
6. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP Min
and 1.0 V.
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4
MC100LVEL38
Table 6. AC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 7)
−40°C
Symbol
fmax
Characteristic
Maximum Toggle Frequency (Figure 4)
Divide by 2
Divide by 4, Divide by 6
Propagation Delay to Output
CLK to Q (Differential)
CLK to Q (Single−Ended)
CLK to Phase_Out (Differential)
CLK to Phase_Out (Single−Ended)
MR to.Q
Within-Device Skew (Note 8)
Part-to-Part
t
S
t
H
V
PP
t
RR
t
PW
t
r
, t
f
Setup Time
Hold Time
Input Swing (Note 9)
Reset Recovery Time
Minimum Pulse Width
CLK
MR
800
700
280
550
Q
0
−
Q
3
All
Min
1.0
0.8
810
710
800
750
510
Typ
1.2
0.82
1010
1010
1000
1050
810
50
75
200
240
150
150
200
250
1000
100
800
700
280
550
150
150
200
250
1000
100
800
700
280
550
Max
Min
1.0
0.8
850
750
840
790
540
25°C
Typ
1.2
0.82
1050
1050
1040
1090
840
50
75
200
240
150
150
200
250
1000
100
Max
Min
1.0
0.8
900
800
890
840
570
85°C
Typ
1.2
0.82
1100
1100
1090
1140
870
50
75
200
240
ps
ps
mV
ps
ps
ps
Max
Unit
GHz
t
PLH
t
PHL
ps
t
SKEW
ps
Q
0
−
Q
3
(Differential)
All
EN to CLK
DIVSEL to CLK
CLK to EN
CLK to Div_Sel
CLK
Output Rise/Fall Times Q (20%
−
80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. V
EE
can vary
±0.3
V.
8. Skew is measured between outputs under identical transitions.
9. V
PP
(min) is minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down
to 100 mV.
Figure 4. Fmax: Voutpp vs Input Frequency per DIV2/4/6
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