EVAL-ADAU1381Z datasheet, PDF - EEWORLD Datasheet

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EVAL-ADAU1381Z: DescriptionInterface - CODECs Low-Noise Stereo w/ EH Recording; CategoryDevelopment board/suite/development tools; File Size664KB，85 Pages; ManufacturerADI; Websitehttps://www.analog.com

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EVAL-ADAU1381Z Overview

Interface - CODECs Low-Noise Stereo w/ EH Recording

EVAL-ADAU1381Z Parametric

Parameter Name	Attribute value
Product Category	Audio IC Development Tools
Manufacturer	ADI
RoHS	Details
Product	Evaluation Boards
Type	Audio CODECs
Tool Is For Evaluation Of	ADAU1381
Operating Supply Voltage	1.8 V to 3.3 V
Packaging	Bulk
Interface Type	I2C, USB
Factory Pack Quantity	1
Unit Weight	2.205 lbs

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Low Noise Stereo Codec with Enhanced

Recording and Playback Processing

ADAU1381

FEATURES

24-bit stereo audio ADC and DAC

400 mW speaker amplifier (into 8 Ω load)

Built-in sound engine for audio processing

Wind noise detection and autofiltering

Enhanced stereo capture (ESC)

Dual-band automatic level control (ALC)

6-band equalizer, including notch filter

Sampling rates from 8 kHz to 96 kHz

Stereo pseudo differential microphone input

Optional stereo digital microphone input pulse-density

modulation (PDM)

Stereo line output

PLL supporting a range of input clock rates

Analog and digital I/O 1.8 V to 3.3 V

Software control via SigmaStudio graphical user interface

Software-controllable, clickless mute

Software register and hardware pin standby mode

32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP

GENERAL DESCRIPTION

The ADAU1381 is a low power, 24-bit stereo audio codec. The

low noise DAC and ADC support sample rates from 8 kHz to

96 kHz. Low current draw and power saving modes make the

ADAU1381 ideal for battery-powered audio applications.

A configurable sound engine provides enhanced record and

playback processing to improve overall audio quality.

The record path includes two digital stereo microphone inputs

and an analog stereo input path. The analog inputs can be

configured for either a pseudo differential or a single-ended

stereo source. A dedicated analog beep input signal can be

mixed into any output path. The ADAU1381 includes a stereo

line output and speaker driver, which makes the device capable of

supporting dynamic speakers.

The serial control bus supports the I

C® or SPI protocols, and

the serial audio bus is programmable for I

S, left-justified, right-

justified, or TDM mode. A programmable PLL supports flexible

clock generation for all standard rates and available master clocks

from 11 MHz to 20 MHz.

APPLICATIONS

Digital still cameras

Digital video cameras

DVDDOUT

FUNCTIONAL BLOCK DIAGRAM

AGND1

AGND2

AVDD1

AVDD2

IOVDD

DGND

REGULATOR

BEEP

PGA

ADAU1381

SOUND ENGINE

LMIC/LMICN/

MICD1

PGA

LMICP

LEFT

ADC

DECIMATION

FILTERS

WIND NOISE

NOTCH FILTER

RMIC/RMICN/

MICD2

PGA

RMICP

PDN

MICBIAS

MICROPHONE

BIAS

PLL

RIGHT

ADC

EQUALIZER

DIGITAL VOLUME

CONTROL

AUTOMATIC LEVEL

CONTROL

SERIAL DATA

INPUT/OUTPUT PORTS

C/SPI

CONTROL PORT

SPP

RIGHT

DAC

SPN

AOUTL

LEFT

DAC

OUTPUT

MIXER

AOUTR

ADC_SDATA/

GPIO1

LRCLK/GPIO3

DAC_SDATA/

GPIO0

BCLK/GPIO2

SCL/CCLK

MCKI

ADDR1/CLATCH

ADDR0/CDATA

SDA/COUT

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

08313-001

ADAU1381

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Record Side Performance Specifications................................... 4

Output Side Performance Specifications................................... 6

Power Supply Specifications........................................................ 8

Typical Power Management Measurements ............................. 9

Digital Filters................................................................................. 9

Digital Input/Output Specifications......................................... 10

Digital Timing Specifications ................................................... 11

Absolute Maximum Ratings.......................................................... 14

Thermal Resistance .................................................................... 14

ESD Caution................................................................................ 14

Pin Configuration and Function Descriptions........................... 15

Typical Performance Characteristics ........................................... 17

System Block Diagrams ................................................................. 20

Theory of Operation ...................................................................... 24

Startup, Initialization, and Power ................................................. 25

Power-Up Sequence ................................................................... 25

Clock Generation and Management........................................ 26

Enabling Digital Power to Functional Subsystems ................ 26

Setting Up the Sound Engine.................................................... 26

Power Reduction Modes............................................................ 26

Power-Down Sequence.............................................................. 26

Clocking and Sampling Rates ....................................................... 27

Core Clock................................................................................... 27

Sampling Rates............................................................................ 27

PLL ............................................................................................... 28

Record Signal Path.......................................................................... 30

Input Signal Path ........................................................................ 30

Analog-to-Digital Converters................................................... 31

Digital Dual-Band Automatic Level Control (ALC) ............. 31

Playback Signal Path ...................................................................... 32

Output Signal Paths ................................................................... 32

Digital-to-Analog Converters................................................... 32

Line Outputs ............................................................................... 32

Speaker Output........................................................................... 32

Control Ports................................................................................... 33

C Port ........................................................................................ 33

SPI Port ........................................................................................ 36

Memory and Register Access.................................................... 36

Serial Data Input/Output Ports .................................................... 38

TDM Modes................................................................................ 38

General-Purpose Input/Outputs .................................................. 40

Sound Engine.................................................................................. 41

Signal Processing........................................................................ 41

Processing Flow .......................................................................... 41

Programming.............................................................................. 41

Parameter Memory .................................................................... 41

Applications Information .............................................................. 42

Power Supply Bypass Capacitors.............................................. 42

GSM Noise Filter ........................................................................ 42

Grounding ................................................................................... 42

Speaker Driver Supply Trace (AVDD2) .................................. 42

Exposed Pad PCB Design ......................................................... 42

Control Register Map..................................................................... 43

Clock Management, Internal Regulator, and PLL Control... 44

Record Path Configuration....................................................... 48

Serial Port Configuration .......................................................... 53

Audio Converter Configuration............................................... 58

Playback Path Configuration.................................................... 63

Rev. B | Page 2 of 84

EVAL-ADAU1381Z Related Products

	EVAL-ADAU1381Z	ADAU1381BCBZ-RL7
Description	Interface - CODECs Low-Noise Stereo w/ EH Recording	Interface - CODECs Low-Noise Stereo w/ EH Recording
Product Category	Audio IC Development Tools	Interface - CODECs
Manufacturer	ADI	ADI
RoHS	Details	Details
Product	Evaluation Boards	Audio CODECs
Type	Audio CODECs	Audio CODEC, Stereo
Interface Type	I2C, USB	SPI, I2C
Factory Pack Quantity	1	2500
Unit Weight	2.205 lbs	0.003210 oz
Packaging	Bulk	Cut Tape

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