Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 8
Chapter 2. Functional Description ...................................................................................................... 10
Principle of NCO ........................................................................................................................................ 10
Lattice NCO Implementation ...................................................................................................................... 11
Sum-of-Angles Memory Reduction ............................................................................................................ 12
Improving Quality of Output ....................................................................................................................... 14
Multi-channel NCO..................................................................................................................................... 16
Quadrature Amplitude Modulation (QAM).................................................................................................. 16
Signal Descriptions ............................................................................................................................................. 17
Latency................................................................................................................................................................ 18
Timing Diagrams ................................................................................................................................................. 18
Chapter 3. Parameter Settings ............................................................................................................ 20
Architecture Tab.................................................................................................................................................. 21
Multi-channel Mode.................................................................................................................................... 22
Wave Characteristics ................................................................................................................................. 22
Phase Correction ....................................................................................................................................... 22
QAM Mode ................................................................................................................................................. 22
FSK/PSK Tab...................................................................................................................................................... 23
FSK Mode .................................................................................................................................................. 23
PSK Mode .................................................................................................................................................. 23
Implementation Tab ............................................................................................................................................ 24
Memory Type ............................................................................................................................................. 24
DSP Block .................................................................................................................................................. 24
Data Output Ports ...................................................................................................................................... 24
Optional I/O Ports....................................................................................................................................... 25
Pipeline Tab ........................................................................................................................................................ 25
Pipeline Options ......................................................................................................................................... 25
Summary Tab...................................................................................................................................................... 26
Chapter 4. IP Core Generation............................................................................................................. 27
Licensing the IP Core.......................................................................................................................................... 27
Getting Started .................................................................................................................................................... 27
IPexpress-Created Files and Top Level Directory Structure............................................................................... 30
Instantiating the Core .......................................................................................................................................... 31
Running Functional Simulation ........................................................................................................................... 31
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 32
Hardware Evaluation........................................................................................................................................... 32
Enabling Hardware Evaluation in Diamond:............................................................................................... 32
Enabling Hardware Evaluation in ispLEVER:............................................................................................. 33
Updating/Regenerating the IP Core .................................................................................................................... 33
Regenerating an IP Core in Diamond ........................................................................................................ 33
Regenerating an IP Core in ispLEVER ...................................................................................................... 33
Chapter 5. Support Resources ............................................................................................................ 35
Lattice Technical Support.................................................................................................................................... 35
Online Forums............................................................................................................................................ 35
Telephone Support Hotline ........................................................................................................................ 35
E-mail Support ........................................................................................................................................... 35
Local Support ............................................................................................................................................. 35
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Lattice Semiconductor
Table of Contents
Internet ....................................................................................................................................................... 35
References.......................................................................................................................................................... 35
LatticeECP/EC ........................................................................................................................................... 35
LatticeECP2M ............................................................................................................................................ 35
LatticeECP3 ............................................................................................................................................... 35
LatticeSC/M................................................................................................................................................ 36
LatticeXP.................................................................................................................................................... 36
LatticeXP2.................................................................................................................................................. 36
Revision History .................................................................................................................................................. 36
Appendix A. Resource Utilization ....................................................................................................... 37
LatticeEC Devices............................................................................................................................................... 37
Ordering Part Number................................................................................................................................ 37
LatticeECP Devices ............................................................................................................................................ 38
Ordering Part Number................................................................................................................................ 38
LatticeECP2 Devices .......................................................................................................................................... 39
Ordering Part Number................................................................................................................................ 39
LatticeECP2M Devices ....................................................................................................................................... 39
Ordering Part Number................................................................................................................................ 39
LatticeECP3 Devices .......................................................................................................................................... 40
Ordering Part Number................................................................................................................................ 40
LatticeSC/M Devices........................................................................................................................................... 40
Ordering Part Number................................................................................................................................ 40
LatticeXP Devices ............................................................................................................................................... 40
Ordering Part Number................................................................................................................................ 40
LatticeXP2 Devices ............................................................................................................................................. 41
Ordering Part Number................................................................................................................................ 41
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NCO IP Core User’s Guide
Chapter 1:
Introduction
Numerically Controlled Oscillators (NCO), also called Direct Digital Synthesizers (DDS), offer several advantages
over other types of oscillators in terms of accuracy, stability and reliability. NCOs provide a flexible architecture that
enables easy programmability such as on-the-fly frequency/phase. NCOs are used in many communications sys-
tems including:
• Digital up/down converters used in 3G wireless and software radio systems
• Digital PLLs
• RADAR systems
• Drivers for optical or acoustic transmissions
• Multilevel FSK/PSK modulators/demodulators
Lattice provides a parameterizable NCO IP core that supports multiple channels and a Quadrature Amplitude Mod-
ulation (QAM) mode, in addition to other usual configurations. The resource utilization and performance trade-off
can be tuned by configuring different parameters of the IP core to obtain the optimal Spurious Free Dynamic Range
(SFDR) result. The Lattice NCO core offers a variety of memory reduction schemes and mechanisms for SFDR
improvement.
Quick Facts
Table 1-1
through
Table 1-9
give quick facts about the NCO IP core for LatticeEC™, LatticeECP™,
LatticeECP2™, LattticeSC™, LatticeSCM™, LatticeXP™, LatticeECP2M™, LatticeXP2™, and Lattice ECP3™
devices.
Table 1-1. NCO IP core for LatticeEC Devices Quick Facts
NCO IP Configuration
Constant FSK/PSK
with 32bit phase res-
olution, 1 channel
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
LUTs
Resource
Utilization
sysMEM EBRs
Registers
MULT18X18ADDSUB
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
1800
3
800
LFEC3E
Variable FSK/PSK
with 32bit phase res-
olution, 1 channel
LatticeEC
LFEC1E
LFEC20E-5F672C
300
2
300
N/A
Diamond
®
1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify
®
Pro for Lattice D-2009.12L-1
Aldec
®
Active-HD
®
8.2 Lattice Edition II
Mentor Graphics
®
ModelSim
®
SE 6.3F
3800
5
1900
LFEC6E
Variable FSK/PSK
with 32bit phase
resolution, 16
channe
IPUG36_02.5, June 2010
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NCO IP Core User’s Guide
Power technology
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