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FMMDT5451

Description
Transistor
CategoryDiscrete semiconductor    The transistor   
File Size284KB,6 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

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FMMDT5451 Overview

Transistor

FMMDT5451 Parametric

Parameter NameAttribute value
MakerJCET
package instruction,
Reach Compliance Codeunknown

FMMDT5451 Preview

Download Datasheet
JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
WBFBP-06C Plastic-Encapsulate Transistors
FMMDT5451
TRANSISTOR
WBFBP-06C
(2×2×0.5)
unit: mm
DESCRIPTION
PNP and NPN Epitaxial Silicon Transistor
FEATURES
Complementary Pair
One 5551-Type NPN, One 5401-Type PNP
Ultra-Small Surface Mount Package
APPLICATION
Ideal for Medium Power Amplification and Switching
For portable equipment:(i.e. Mobile phone,MP3, MD,CD-ROM,
DVD-ROM, Note book PC, etc.)
MARKING: KNM
1
KNM
E1,B1,C1=NPN 5551 Section
E2,B2,C2=PNP 5401 Section
5551 MAXIMUM RATINGS* T
A
=25℃ unless otherwise noted
Symbol
V
CBO
V
CEO
V
EBO
I
C
P
C
RθJA
T
J
T
stg
Parameter
Value
180
160
6
0.2
0.15
625
150
-55-150
Units
V
V
V
A
W
K/W
Collector-Base Voltage
Collector-Emitter Voltage
Emitter-Base Voltage
Collector Current -Continuous
Collector Dissipation
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature range
5401 MAXIMUM RATINGS* T
A
=25℃ unless otherwise noted
Symbol
V
CBO
V
CEO
V
EBO
I
C
P
C
RθJA
T
J
T
stg
Collector- Base Voltage
Collector-Emitter Voltage
Emitter-Base Voltage
Collector Current -Continuous
Collector Dissipation
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature range
Parameter
Value
-160
-150
-5
-0.2
Units
V
V
V
A
0.15
625
150
-55-150
W
K/W
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