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DTC114WCA

Description
Rated power: 200mW Collector current Ic: 100mA Collector-emitter breakdown voltage Vce: 50V Transistor type: NPN - pre-biased NPN, Vcc=50V, Io=100mA
CategoryDiscrete semiconductor    The transistor   
File Size10MB,15 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/
Environmental Compliance

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

Download Datasheet Parametric View All

DTC114WCA Overview

Rated power: 200mW Collector current Ic: 100mA Collector-emitter breakdown voltage Vce: 50V Transistor type: NPN - pre-biased NPN, Vcc=50V, Io=100mA

DTC114WCA Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerJCET
package instruction,
Reach Compliance Codeunknown
Maximum collector current (IC)0.1 A
Minimum DC current gain (hFE)24
Number of components1
Polarity/channel typeNPN
Maximum power dissipation(Abs)0.2 W
surface mountYES
Base Number Matches1

DTC114WCA Preview

Download Datasheet
JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
JC T
Digital Transistors (Built-in Resistors)
DTC114WM/DTC114WE/DTC114WUA
DTC114WKA /DTC114WCA/DTC114WSA
DIGITAL TRANSISTOR (NPN)
·Equivalent
Circuit
FEATURES
Built-in bias resistors enable the configuration of an inverter circuit
without connecting external input resistors(see equivalent circuit)
The bias resistors consist of thin-film resistors with complete isolation to
allow negative biasing of the input.They also have the advantage of
almost completely eliminating parasitic effects
Only the on/off conditions need to be set for operation, making device design easy
PIN CONNENCTIONS and MARKING
DTC114WM
SOT-723
1. IN
2. GND
3. OUT
DTC114WE
SOT-523
1. IN
2. GND
3. OUT
MARKING:84
MARKING:84
DTC114WUA
SOT-323
1. IN
2. GND
3. OUT
DTC114WKA
SOT-23-3L
1. IN
2. GND
3. OUT
MARKING:84
MARKING:84
DTC114WCA
SOT-23
1. IN
2. GND
3. OUT
DTC114WSA
TO-92S
1. GND
2. OUT
3. IN
MARKING:84
www.cj-elec.com
1
F,Oct,2014
C,Mar,2012
C,Mar,2012
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