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CD4094BM/TR

Categorylogic    The 4000 series logic chip   
File Size336KB,5 Pages
ManufacturerGuangdong Huaguan Semiconductor Co., Ltd.
Websitehttp://www.hgsemi.net/
Guangdong Huaguan Semiconductor Co., Ltd. was established in 2011. It is a quasi-high-tech enterprise specializing in the research and development, packaging, testing and sales of semiconductor devices. The company has an internationally advanced level of semiconductor discrete devices and integrated circuit packaging and testing production lines, and a technical team with rich experience in the design, packaging and testing of semiconductor devices. It has established long-term strategic cooperative relations with first-class companies in the same industry, and has formed a professional technical development team to engage in the development of new products and new technologies. The company's R&D project products include power management, operational amplifiers, audio amplifiers, interfaces and drivers, logic devices, memory, time base and clock, data acquisition, MOSFT and special circuits, which are mainly used in automotive electronics, instrumentation, network communications, industrial automation, LED lighting, switching power supplies, smart home appliances, gold card projects, smart transportation and other fields. Huaguan products are positioned as high-end quality, and have been well received by users in recent years. It is currently a high-end quality brand in the industry; HGSEMI&HGC is Huaguan's own brand. The establishment of an independent brand is more conducive to our service to customers, promoting the development of the company, and becoming a leading manufacturer in China's semiconductor industry.
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CD4094BM/TR Preview

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CD4094B
8-Bit Shift Register/Latch with 3-STATE Outputs
General Description
The CD4094B consists of an 8-bit shift register and a 3-
STATE 8-bit latch. Data is shifted serially through the shift
register on the positive transition of the clock. The output of
the last stage (Q
S
) can be used to cascade several
devices. Data on the Q
S
output is transferred to a second
output, Q′
S
, on the following negative clock edge.
The output of each stage of the shift register feeds a latch,
which latches data on the negative edge of the STROBE
input. When STROBE is HIGH, data propagates through
the latch to 3-STATE output gates. These gates are
enabled when OUTPUT ENABLE is taken HIGH.
Features
s
Wide supply voltage range:
s
High noise immunity:
s
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
s
3-STATE outputs
3.0V to 18V
0.45 V
DD
(typ.)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOP
Top View
Truth Table
Clock
Output
Enable
0
0
1
1
1
1
X
X
0
1
1
1
X
X
X
0
1
1
Strobe
Data
Parallel Outputs
Q1
Hi-Z
Hi-Z
0
1
Q
N
Hi-Z
Hi-Z
Q
N
−1
Q
N
−1
Serial Outputs
Q
S
(Note 1)
Q7
No Change
Q7
Q7
Q7
Q′
Σ
No Change
Q7
No Change
No Change
No Change
Q7


X
=
Don't Care
=
HIGH-to-LOW
=
LOW-to-HIGH






No Change No Change
No Change No Change No Change
Note 1:
At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q
S
.
http://www.hgsemi.com.cn
1
2018 JUN
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