3DD13003(TO-126) datasheet, PDF

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3DD13003(TO-126): DescriptionTransistor; CategoryDiscrete semiconductor The transistor; File Size33KB，1 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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3DD13003(TO-126) Overview

Transistor

3DD13003(TO-126) Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknow
Maximum collector current (IC)	1.5 A
Configuration	Single
Minimum DC current gain (hFE)	5
Maximum operating temperature	150 °C
Polarity/channel type	NPN
Maximum power dissipation(Abs)	1.25 W
surface mount	NO
Nominal transition frequency (fT)	5 MHz
Base Number Matches	1

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

TO-126 Plastic-Encapsulate Transistors

3DD13003

FEATURES

Power dissipation

CM:

1.25

W (Tamb=25℃)

1. BASE

2. COLLECTOR

3. EMITTER

TRANSISTOR (NPN)

TO-126

Collector current

1.5 A

CM:

Collector-base voltage

700 V

(BR)CBO

Operating and storage junction temperature range

, T

stg

: -55℃ to +150℃

ELECTRICAL CHARACTERISTICS (Tamb=25℃

Parameter

Collector-base breakdown voltage

Collector-emitter breakdown voltage

Emitter-base breakdown voltage

Collector cut-off current

Emitter cut-off current

Symbol

V(BR)

CBO

V(BR)

CEO

V(BR)

EBO

CBO

CEO

EBO

FE(1)

DC current gain

FE(2)

Collector-emitter saturation voltage

Base-emitter saturation voltage

Base-emitter voltage

Transition frequency

Fall time

Storage time

(sat)

123

unless otherwise specified)

Test

conditions

MIN

700

400

1000

500

1000

1.2

0.5

2.5

MHz

µs

TYP

MAX

UNIT

µA

Ic= 1000

A, I

Ic= 10mA, I

= 1000

A, I

= 700V, I

= 400V, I

= 9V, I

= 2V, I

= 0.5 A

= 10V, I

= 0.5 mA

=1000mA,I

= 250 mA

=1000mA, I

= 250mA

= 2000 mA

=10V, Ic=100mA

f =1MHz

=1A, I

=-I

=0.2A

=100V

CLASSIFICATION OF H

FE(1)

Rank

Range

8-10

10-15

15-20

20-25

25-30

30-35

35-40

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