2SC1318AS datasheet, PDF - EEWORLD Datasheet

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2SC1318AS: DescriptionTransistor; CategoryDiscrete semiconductor The transistor; File Size144KB，2 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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2SC1318AS Overview

Transistor

2SC1318AS Parametric

Parameter Name	Attribute value
Maker	JCET
package instruction	,
Reach Compliance Code	unknow
Maximum collector current (IC)	0.5 A
Configuration	Single
Minimum DC current gain (hFE)	170
Maximum operating temperature	150 °C
Polarity/channel type	NPN
Maximum power dissipation(Abs)	0.75 W
surface mount	NO
Base Number Matches	1

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

TO-92 Plastic-Encapsulate Transistors

2SC1318A

TRANSISTOR (NPN)

TO-92

FEATURES

· Collector output capacitance :

Cob=11

(TYP),20

(MAX)

MAXIMUM RATINGS (T

=25

℃

unless otherwise noted)

Symbol

CBO

CEO

EBO

stg

Parameter

Collector-Base Voltage

Collector-Emitter Voltage

Emitter-Base Voltage

Collector Current -Continuous

Collector Power Dissipation

Junction Temperature

Storage Temperature

Value

500

750

150

-55-150

Units

℃

EMITTER

COLLECTOR

BASE

1 2 3

ELECTRICAL CHARACTERISTICS (Tamb=25℃ unless otherwise specified)

Parameter

Collector-base breakdown voltage

Collector-emitter breakdown voltage

Emitter-base breakdown voltage

Collector cut-off current

Symbol

(BR)CBO

(BR)CEO

(BR)EBO

CBO

FE(1)

DC current gain

FE(2)

Collector-emitter saturation voltage

Base-emitter saturation voltage

Transition frequency

Collector output capacitance

CE(sat)

BE(sat)

=10V,I

=500mA

=300mA,I

=30mA

=300mA,I

=30mA

=10V,I

=50mA,f=200MHz

=10V,I

=0,f=1MHz

120

0.6

1.5

MHz

Test

conditions

MIN

0.1

340

TYP

MAX

UNIT

μA

=10μA,I

=2mA,I

=10μA,I

=20V,I

=10V,I

=150mA

CLASSIFICATION OF

Rank

Range

FE(1)

85-170

120-240

170-340

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