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SPC574S64E3CEFAY

Description
e200z4 series Microcontroller IC 32-bit 140MHz 1.5MB (1.5M x 8) Flash 100-eTQFP (10x10)
Categorysemiconductor    The embedded processor and controller   
File Size2MB,77 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

SPC574S64E3CEFAY Overview

SPC574S64E3CEFAY is a next-generation microcontroller family based on the PowerArchitecture embedded category. The SPC574S64E3CEFAY family is the latest achievement in integrated automotive application controllers. It is an expanding family of automotive products designed to address the next wave of automotive chassis and safety electronics applications. The automotive controller family's advanced, cost-effective host processor core qualifies for the Power Architecture Embedded category and implements only VLE (Long Code) APUs, providing improved code density. It operates at speeds up to 140 MHz and provides low power consumption optimized for high-performance processing. It leverages the available development infrastructure for current Powerarchitecture devices, supported by software drivers, operating systems and configuration code to help users implement it.

SPC574S64E3CEFAY Parametric

Parameter NameAttribute value
categorysemiconductor;The embedded processor and controller
MakerSTMicroelectronics
seriesAutomotive, AEC-Q100, SPC57 S
Packagetray
core processore200z4
Kernel specifications32-bit dual core
speed140MHz
ConnectivityCANbus,FlexRay,LINbus,SPI,UART/USART
PeripheralDMA,LVD,POR,WDT
Number of I/Os64
Program storage capacity1.5MB(1.5M x 8)
Program memory typeflash memory
EEPROM capacity64K x 8
RAM size96K x 8
Voltage - Power supply (Vcc/Vdd)3.135V ~ 5.25V
data converterA/D 32x12b SAR
Oscillator typeinternal
Operating temperature-40°C ~ 125°C(TA)
Installation typesurface mount type
Package/casing100-TQFP Exposed Pad
Supplier device packaging100-eTQFP(14x14)
Basic product numberSPC574

SPC574S64E3CEFAY Preview

Download Datasheet
SPC574S60E3, SPC574S64E3
32-bit Power Architecture microcontroller for automotive ASILD
applications
Datasheet
-
production data
– Cyclic redundancy check (CRC) unit
8 enhanced 12-bit SAR analog converters
– 2 sets of: 3 ADCs and one supervisor ADC
– 1.5 µs conversion time at 12 MHz
– Up to 32 physical channels
– Dual Programmable CTU
4 general purpose eTimer units (6 channels
each)
4 FlexPWM units
– 2 (4 channels each) used for motor control
with hardware synchronization between the
control systems
– 2 (2 channels each) used for SWG
emulation
Communication interfaces
– 4 LINFlexD modules
– 4 deserial serial peripheral interface (DSPI)
modules
– 2 MCAN interfaces with advanced shared
memory scheme (808 x 32-bit words for
MCAN0 and 520 x 32-bit words for
MCAN1) and CAN-FD support
– 1 FlexRay module with 2 channels, 128
message buffers
– 2 SENT interfaces (3 channels each)
Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
domain for computational shell
Nexus Class 3 debug and trace interface
On-chip CAN/UART Bootstrap loader with
BAF. Physical Interface (PHY) can be UART
Advanced and flexible supply scheme
– On-chip voltage regulator for 1.2 V core
logic supply. Bypass mode supported for
external 1.2 V core logic supply
– 3.3 V or 5 V IO and ADC supply (2
independent power domains available)
Junction temperature range -40 °C to 150 °C
eTQFP100 (14 x 14 x 1.0 mm)
Features
AEC-Q100 qualified
High performance e200z4d dual core
– 32-bit Power Architecture technology CPU
– Core frequency as high as 140 MHz
– Dual issue 5-stage pipeline in-order
execution core
– Variable Length Encoding (VLE)
– Core MPU
– Floating Point, End-to-End Error Correction
– 8 KB instruction cache with error detection
code
– 32 KB local data RAM and 4 KB data cache
along with 8 KB instruction cache
1600 KB (1.5 MB code + 64 KB data) on-chip
flash memory: supports read during program
and erase operations, and multiple blocks
allowing EEPROM emulation
128 KB on-chip RAM (96 KB on chip
RAM + 32 KB local data RAM)
Multi-channel direct memory access controller
(eDMA) with 32 channels
Comprehensive new generation ASILD safety
concept
– ASILD SEooC approach (Safety Element
out of Context)
– FCCU for collection and reaction to failure
notifications
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
– End-to-end Error Correction Code
(e2eECC) logic
February 2020
This is information on a product in full production.
DS10601 Rev 6
1/77
www.st.com

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