Peak voltage sample and hold circuit

Peak voltage sample and hold circuit : The peak voltage sample and hold circuit is shown in Figure 12-50. The peak voltage sampling and holding circuit consists of
a sampling and holding chip LF398 and a voltage comparator LM311 . The output voltage and input voltage of LF398
are compared through LM3J1 when U. >Uo hour. LM311 outputs high level and sends it to pin 8 of the logic control terminal of LF398, so that LF398 is in the sampling state.
When Ul reaches the peak value and decreases, U, <U. , the voltage comparator LM311 outputs a low level, and the logic control terminal of LF398 is set to a low level
, so that the LF398 is in a holding state. Since LM311 uses an open-collector output, a pull-up resistor needs to be connected.
The pulse sent from the output end of the overvoltage detection circuit controls the conduction of the circuit switch. When there is no overvoltage, the sampling capacitor is discharged. Otherwise, the sampling circuit keeps tracking
the changes in the peak value.