Dual CAN bus and Ethernet monitoring circuit design guide—Circuit diagrams read every day (93)
Source: InternetPublisher:MartinFowler Updated: 2021/11/05
At present, the most commonly used field bus is CAN bus. CAN bus has been widely used in intelligent communication networks due to its high reliability, low cost, flexible application and many other advantages. However, the limitation of transceiver driving capability is not suitable for long-distance data transmission and remote control. control. Ethernet has mature technology, fast communication speed, rich software and hardware products, and comprehensive peripheral technical support. It can use the network for long-distance communication, but there are still some unresolved problems in industrial control. Combining the advantages and disadvantages of CAN bus and Ethernet, this paper studies an on-site monitoring module based on dual CAN bus and Ethernet suitable for ship monitoring systems. This module can be installed in the power distribution switch cabinet and can perform current, voltage and switching operations nearby. Collect status information, perform data processing independently, and realize functions such as measurement, protection, and control. It can communicate with other intelligent nodes through redundant dual CAN buses, and upload important data to the monitoring station through Ethernet to assist the monitoring station in completing monitoring and control functions. As a link between the power distribution network and the monitoring network, it has good development and application prospects.
Hardware system of on-site monitoring module
In the on-site monitoring module, a large amount of on-site real-time data needs to be collected and processed, and transmitted to the centralized monitoring station in a timely and rapid manner. That is, the specific data of the entire control process is provided to the centralized monitoring station. At the same time, judgment processing must be completed and passed through the output module. To send various control commands, considering its functional complexity, a hardware solution of DSP+FPGA dual controller is adopted. The hardware structure principle is shown in Figure 1.
1) A/D chip This system uses AD7865 as the A/D chip. This chip is a high-speed 14-bit A/D converter that simultaneously samples 4 input channels and has 4 sample and hold amplifiers. Its advantage is that it can truly realize synchronous sampling of multi-channel signals and maintain the phase relationship of each channel signal. It has on-chip clock, read and write enable logic, multiple channel selection methods and internal accurate 2.5V reference voltage, making its interface with high-speed processors very simple. This system is equipped with a total of 4 AD7865s, which can simultaneously sample up to 16 channels of analog data.
2) Electromagnetic isolation The input and output of all switching values adopt electromagnetic isolation technology, which can effectively improve the anti-interference ability. This system selected 16 pieces of 4-channel integrated electromagnetic isolation chip ADUM1410, so that the module can complete up to 32 inputs and 32 channels at the same time. Output data collection.
3) FPGA This system uses EP1C6PQ240 as the auxiliary control chip of the system. The chip has 5980 logic units. The embedded memory block has a column of M4K blocks. Each M4K block can be composed of various memories, including dual-port, single-port RAM, and ROM. and FIFO, etc., the I/O unit contains a bidirectional I/O buffer and three registers, has 2 phase-locked loops and 8 independent system clocks, the number of chip pins is 240, and the number of available pins is 185. FPGA mainly completes data input and output control and data preprocessing functions. All switching signals are sent to the FPGA. All analog signals are converted into digital signals by the A/D chip and then sent to the FPGA. The FPGA needs to provide control signals to the A/D chip to control the reading and writing of the A/D chip. All The data is preprocessed by FPGA and read by DSP.
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