A design plan for a serial communication interface circuit

Basic UART communication only requires two signal lines (RXD, TXD) to complete the mutual communication of data. Reception and transmission are in full-duplex form, where TXD is the UART transmitter and RXD is the UART receiver. The basic characteristics of UART are: there are two states on the signal line, which can be distinguished by logic 1 (high level) and logic 0 (low level). The data line should remain in a logic high state while the transmitter is idle. The transmitter starts a character transmission by sending a start bit. The start bit puts the data line in a logic 0 state, prompting the receiver that data transmission is about to begin. The data bits are generally 8-bit numbers per byte (there are also 6-bit and 7-bit cases), with the low-order bit (LSB) first and the high-order bit (MSB) last. The check bit is generally used to determine whether the received data bits have errors, usually parity check. The stop bit is at the end and is used to mark the end of a character transmission by UART. It corresponds to the logic 1 state and UART data frame format.

UART (UniversalAnynchrONousReceiverTransmitter, Universal Asynchronous Receiver Transmitter) is one of the widely used serial data transmission protocols, and its application range covers computer peripherals, industrial control automation and other occasions. Although the USB transmission protocol has higher performance than the UART protocol, the circuit is complex and difficult to develop, and most microprocessors only integrate UART. Therefore, UART is still the main protocol for serial communication between digital systems.

 With the widespread application of FPGA, FPGA is often required to communicate serially with other digital systems. Dedicated UART integrated circuits such as 8250, 8251, etc. are relatively complex, because the dedicated UART integrated circuit must consider both asynchronous sending and receiving functions and Compatible with RS232 interface design, in actual applications, only the basic functions of UART are often needed. Using dedicated chips will cause a waste of resources and increase costs. The required UART functions can be integrated into the FPGA to realize direct communication between the FPGA and other digital systems, thus simplifying the entire system circuit and improving reliability, stability and flexibility.

UART function implementation

UART can be decomposed into 3 sub-modules: baud rate generator module; sending module; receiving module. The function of UART is mainly programmed by VHDL hardware description language, which is the graphic element SCI generated after compilation. It includes the most important part of UART, namely the sending module and the receiving module. SCI's external port lines can be divided into 3 categories:

The first is the interface with the digital system, including data DATA[7.0], chip select CS, read and write RD, WR, status RDFULL, TDEMPTY. The function completed by this part of the interface is to write the data to be sent into SCI or read out from SCI Data received.

The second is the serial communication interface 2 lines RXD and TXD, where RXD is the receiving data line and TXD is the sending data line. Therefore, SCI implements a full-duplex communication design.

The third is the system control lines RESET and CLK. RESET is the module reset input, and CLK is the module clock input. The baud rate of communication is determined by CLK (the actual baud rate is CLK/4).

RDFULL and TDEMPTY are two status flag bits. RDFULL is the input register full flag. The high level indicates that a valid data has been received and stored in the input data register. When CS and RD are valid, the data will be read out and become low level. invalid.

TDEMPTY is the output register empty flag. A high level indicates that the data effectively written to the output register by CS and WR has been sent. Additional data to be sent can be written to the output register. A low level indicates that the data is currently being sent.

Send module design

The sending module is composed of sending control process, data writing process, parallel/serial conversion process, status operation process and other processes. Among them, the most important one is the sending control process. In the sending control process, a 6-bit variable scit_v is declared, and its value (state machine) state controls the entire sending process. scit_v is divided into the high four bits of sh_t and the low two bits of sl_. tscit_v is assigned an initial value of 28 (011100B) after the system is reset. scit_v is incremented every time a clock comes, and sh_t is incremented every four clocks. When sh_t is When 0111B, the start bit is sent, and when sh_t is 1000~1111B, 8-bit data is sent.