FPGA Simple Design Method Classic Case 3 [1241003385]

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FPGA Simple Design Method Classic Case 3 [1241003385] [Copy link]

Classic case of minimalist design method3

Case3.When receiving en1=1, dout generates a high level pulse of 3 clock cycles; when receiving en2==1, dout generates a high level pulse of 2 cycles. The waveform above shows the described function. At the 3rd clock rising edge, en1==1 is received, so dout changes to 1 and lasts for 3 clock cycles; at the 9th clock rising edge, en2==1 is seen, so dout changes to 1 and lasts for 2 clock cycles. Note that en1==1 and en2==1 appear in no order. Some readers may ask, what should we do if en1==1 and en2==1 appear at the same time, or if en1==1 or en2==1 appears during dout==1? Please do not consider this situation. This case assumes that this situation will never occur. When Mingdeyang specifies the module division, it requires clear coordination between modules. Otherwise, each module has to handle all situations, which is quite complicated. When you see a number greater than 1, you know to count. The recommended counting method is as follows: The counter cnt counts the number of dout==1. Do not consider using two counters to count en1 and en2 respectively. This is because even if two counters are used, these two counters are not counting at the same time. Not counting at the same time means that they can be merged. We encountered a problem when confirming how many counters there are. Because this counter is sometimes cleared when it counts to 3 (the waveform triggered by en1==1), and sometimes cleared when it counts to 2 (the waveform triggered by en2==1). At this time, we suggest you use the variable x instead, that is, count to x. Note that Verilog does not have the concept of variables. This variable is a design concept proposed by Ming Deyang. x is essentially a signal. What is the use of introducing variables? It is convenient to design a counter. The condition for adding 1 to the counter is dout==1, and it ends when it counts x. Therefore, the code is as follows: We can even write the code for dout. The condition for dout to become 1 is: en1==1 or en2==1; the condition for becoming 0 is: the counter has finished counting. So the code is as follows:

Let's design the variable x. We know that when the counter en1==1 is triggered, it will be cleared when it counts to 3, and when en2==1 is triggered, it will be cleared when it counts to 2. For this reason, we add a signal flag_sel to distinguish these two situations. flag_sel==0 means it is triggered by en1==1, and flag_sel==1 means it is triggered by en2==1. The waveform is as follows:

The condition for flag_sel to change to 0 is when en1==1, and the condition for flag_sel to change to 1 is when en2==1. For this purpose, the code for flag_sel is as follows. With flag_sel, it is easy for us to distinguish the value of x. When flag_sel is 0, x is 3 (3 zeros); when flag_sel is 1, x is 2 (2 zeros). At this time, you need to use combinational logic to design x, otherwise you will make a mistake. The code is as follows: So far, the main program of this project has been designed. In this question, we used the variable x, which is the variable method in Ming Deyang's minimalist design method.

Define the name of the module as my_ex3. And we already know that the module has 5 signals: clk, rst_n, en1, en2 and dout. To this end, the code is as follows:

Among them, clk, rst_n, en1 and en2 are input signals, dout is the output signal, and 5 signals are all 1bit. Based on this information, we supplement the input and output port definitions. The code is as follows:

Next, define the signal type.

cnt is a signal generated by always, so the type is reg. The maximum value of cnt count is 2, which needs to be represented by 2 lines, that is, the bit width is 2 bits. add_cnt and end_cnt are both designed in the assign method, so the type is wire. And its value is 0 or 1, which can be represented by 1 line. Therefore, the code is as follows: dout is designed in the always method, so the type is reg. And its value is 0 or 1, 1 can be represented by a line. Therefore, the code is as follows:

flag_sel is designed in the always way, so the type is reg. And its value is 0 or 1, 1 can be represented by a line. Therefore, the code is as follows:

x is designed in the always way, so the type is reg , and its maximum value is 3 , which can be represented by 2 lines. Therefore, the code is as follows:

So far, the design of the entire code has been completed. The overall code is as follows:

1 2 3 4 5 6 [align=left ]7 8 9 10 11 12 13 14 15 16 17 18[/align ] 19 20 21 22 23 24 25 26 27 28 [/td] [td= 442] module my_ex3( clk , rst_n , en1 , en2 , dout ); input clk ;[/align ] input rst_n ; input en1 ; input en2 ; output dout ; reg [ 1:0] cnt ; wire add_cnt ; wire end_cnt ; reg dout ; reg flag_sel ; reg [ 1:0] x ; always @(posedge clk or negedge rst_n)begin if(!rst_n)begin cnt <= 0; end [align=left ] else if(add_cnt)begin if(end_cnt) cnt <= 0; else cnt <= cnt + 1; end end assign add_cnt = dout==1; [ /align] assign end_cnt = add_cnt && cnt==x-1 ; always @( posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout <= 0; end[ /align] else if(en1==1 || en2==1)begin dout <= 1; end[/align ] else if(end_cnt)begin dout <= 0; end end [/ align] always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin flag_sel <= 0; end else if(en2==1 )begin flag_sel <= 1; end else if(en1==1)begin [align =left] flag_sel <= 0; end always @(*)begin if(flag_sel==0) x = 3; else x = 2; end ] endmodule

[ Summary: When designing, we should not be influenced by specific numbers, but carefully identify the consistent actions of the signal, and then use the variable method to Design. This allows you to design sophisticated code.rst_n)begin

cnt <= 0;

end

else if(add_cnt)begin

[align=left ] if(end_cnt)

cnt <= 0;

else

cnt <= cnt + 1;

[ align=left] end

end

assign add_cnt = dout==1;

assign end_cnt = add_cnt && cnt==x-1;

always @(posedge clk or negedge rst_n)begin[ /align]

if(rst_n==1'b0)begin

dout <= 0;

end

else if (en1==1 || en2==1)begin

dout <= 1;

end

else if(end_cnt )begin

dout <= 0;

end

end

[ align=left]

always @(posedge clk or negedge rst_n)begin

if(rst_n==1'b0)begin

[align=left ] flag_sel <= 0;

end

else if(en2==1)begin

flag_sel <= 1;

end[/ align]

else if(en1==1)begin

flag_sel <= 0;

end

end

always @(*)begin

if(flag_sel==0)

x = 3;

else

x = 2;

end

[ align=left]endmodule

[/td] [/tr] Summary: When designing, We should not be influenced by specific numbers, but carefully identify the consistent actions of the signal, and then use the variable method to design. In this way, we can design sophisticated code.rst_n)begin

cnt <= 0;

end

else if(add_cnt)begin

[align=left ] if(end_cnt)

cnt <= 0;

else

cnt <= cnt + 1;

[ align=left] end

end

assign add_cnt = dout==1;

assign end_cnt = add_cnt && cnt==x-1;

always @(posedge clk or negedge rst_n)begin[ /align]

if(rst_n==1'b0)begin

dout <= 0;

end

else if (en1==1 || en2==1)begin

dout <= 1;

end

else if(end_cnt )begin

dout <= 0;

end

end

[ align=left]

always @(posedge clk or negedge rst_n)begin

if(rst_n==1'b0)begin

[align=left ] flag_sel <= 0;

end

else if(en2==1)begin

flag_sel <= 1;

end[/ align]

else if(en1==1)begin

flag_sel <= 0;

end

end

always @(*)begin

if(flag_sel==0)

x = 3;

else

x = 2;

end

[ align=left]endmodule

[/td] [/tr] Summary: When designing, We should not be influenced by specific numbers, but carefully identify the consistent actions of the signal, and then use the variable method to design. In this way, we can design sophisticated code.

end

else if(en2==1)begin

flag_sel <= 1;

end[/ align]

else if(en1==1)begin

flag_sel <= 0;

end

end

always @(*)begin

if(flag_sel==0)

x = 3;

else

x = 2;

end

[ align=left]endmodule

[/td] [/tr] Summary: When designing, We should not be influenced by specific numbers, but carefully identify the consistent actions of the signal, and then use the variable method to design. In this way, we can design sophisticated code.

end

else if(en2==1)begin

flag_sel <= 1;

end[/ align]

else if(en1==1)begin

flag_sel <= 0;

end

end

always @(*)begin

if(flag_sel==0)

x = 3;[ /align]

else

x = 2;

end

endmodule

[/td] [/tr] Summary: When designing, We should not be influenced by specific numbers, but carefully identify the consistent actions of the signal, and then use the variable method to design. In this way, we can design sophisticated code.

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