Some issues with the SG3525A chip

shaorc

【If you don't understand, ask】 As shown in the figure, the internal structure of the driver chip SG3525A 【1】Originally, pins 1 and 2 are the input terminals of the error amplifier, but before the input to the PWM comparator in the figure, there is a 9-pin compensation. What is this compensation for? 【2】Ct and Rt on pins 5 and 6 can be seen in many chips. They are said to determine the frequency of the oscillator. Take this figure as an example. Why do we need this oscillator? What is its function? 【3】The latch module in the figure is an RS trigger, right? Its function is to store PWM waves? What is the difference between the signal output from its R terminal and the signal output from its right side? 【4】The document says: "The output of the oscillator is divided into two paths. One path is sent to the bistable trigger and two NOR gates in the form of a clock pulse; the other path is sent to the comparator's non-inverting input in the form of a sawtooth wave." The bistable trigger in Figure 1 refers to the F/F one, right? But the sawtooth wave sent to the comparator is not output from the oscillator output. The figure shows that it is output from the CT pin to the comparator. Figure 1 Figure 2

maychang

【2】Ct and Rt at pins 5 and 6 can be seen in many chips. They determine the frequency of the oscillator. For example, in this figure, why do we need this oscillator? What is its function? SG3525 is a PWM control chip. PWM means pulse width modulate, or "pulse width modulation". Pulse width modulation is to change the pulse width by fixing the pulse frequency and changing the pulse duty cycle. Since it is a "pulse width modulation" working mode with a fixed pulse frequency, of course there must be such a frequency (square wave), and a relaxation oscillator must be used to generate this square wave. Ct and Rt are the components that control this frequency.

maychang

【1】Originally, pins 1 and 2 are the input terminals of the error amplifier. However, before the input to the PWM comparator in the figure, there is a compensation pin at pin 9. What is this compensating for? Pin 9 is the output terminal of the two op amps on the chip. When the op amp is in use, there must be feedback from the output terminal to the input terminal. This feedback circuit is determined by the user. Pin 9 is set to lead out the output signal of the op amp.

maychang

[3] The latch module in the figure is an RS trigger, right? Is it used to store PWM waves? What is the difference between the signal output from its R terminal and the signal output from its right side? Latches are usually called "latch". The R above and the S below are not output terminals, but input terminals of the latch.

maychang

【4】The document says: "The output of the oscillator is divided into two paths, one is sent to the bistable trigger and two NOR gates in the form of clock pulses; the other is sent to the non-inverting input of the comparator in the form of sawtooth waves." The bistable trigger in Figure 1 refers to the F/F one, right? But the sawtooth wave sent to the comparator is not output from the oscillator output. The figure shows that it is output from the CT pin to the comparator. This statement is correct. The two ends of Ct are sawtooth waves, and the 5th pin is connected to the comparator input inside the chip.

shaorc

maychang posted on 2018-9-14 16:50 【1】Originally, pins 1 and 2 are the input terminals of the error amplifier, but before the input to the PWM comparator in the figure, there is a compensation pin 9, which...

Pin 9 is used for op amp feedback. Generally, capacitors and resistors are connected to the negative pole of the op amp to prevent oscillation. Can I understand it this way?

shaorc

maychang posted on 2018-9-14 16:55 【4】The document says: "The output of the oscillator is divided into two paths, one is sent to the bistable trigger and two NOR gates in the form of clock pulses; the other is sent to the bistable trigger and two NOR gates in the form of sawtooth...

The function of the oscillator is known, which is to output a fixed PWM frequency, but how to make it output in the form of constant pulse and sawtooth wave respectively? Also, you said that the two ends of CT are sawtooth waves, and are internally connected to the comparator input. Baidu's information says that it has the function of increasing the dead time. I don't understand.

shaorc

maychang posted on 2018-9-14 16:52 【3】The latch module in the figure is an RS trigger, right? Is it used to store PWM waves? What is the difference between the signal output from its R end and the signal output from its right side...

Why do we need to set up a latch to store PWM waves?

maychang

shaorc posted on 2018-9-15 14:58 Pin 9 is used for op amp feedback. Generally, capacitors and resistors are connected to the negative pole of the op amp to prevent oscillation. Can I understand it this way?

It is not only to prevent oscillation, but more importantly to control the voltage gain of the amplifier. Whether to prevent oscillation depends on the requirements of the entire feedback loop.

maychang

shaorc posted on 2018-9-15 15:01 We know the function of the oscillator, which is to output a fixed PWM frequency, but how can it be output in the form of a constant pulse and a sawtooth wave respectively? And...

But how can it be output in the form of a constant pulse and a sawtooth wave respectively? The internal oscillator of SG3525 outputs a sawtooth wave, that is, the voltage across Ct. This sawtooth wave is used by the comparator to compare with a fixed level (that is, the output of the op amp). The rectangular wave output by the internal oscillator is used for flipping the trigger marked as F/F in the figure. As for how to output as a rectangular pulse and a sawtooth wave respectively, it is determined by the structure of the oscillator. There are such examples in the analog circuit textbook.

maychang

shaorc posted on 2018-9-15 15:01 We know the function of the oscillator, which is to output a fixed PWM frequency, but how to make it output in the form of constant pulse and sawtooth wave respectively? And...

Baidu's information says that it has the function of increasing the dead time, but I don't understand. To understand how the dead time is formed, you need to understand how the oscillator works. In fact, the dead time is the output pulse of the oscillator through an internal triode and then output from pin 7, and then through an external resistor to control the discharge time of the capacitor.

maychang

shaorc posted on 2018-9-15 15:04 Why do we need to set up a latch to store PWM waves?

To understand the function of this latch, we must first understand the function of the part in the dotted box in the first post. This part is two four-input NOR gates. The NOR gate outputs low when any input is high. Under-Voltage Lockout is a latch. If the power supply voltage for the chip is too low, the Under-Voltage Lockout output is high, the two sets of transistor totem poles are turned on, and the output of pin 11 or pin 14 is low. The F/F two-way output is complementary, so the upper and lower paths cannot be high at the same time. The latch output is also connected to the four-input NOR gate. The latch high-level output also makes the upper and lower outputs low. The high level of the chip 10-pin input will turn on an internal transistor, which discharges the external capacitor connected between the 8-pin and the ground. The high level of the 10-pin simultaneously turns off the two four-input NOR gates. The charging process of the external capacitor at the 8-pin is the soft start process of the SG3525 (the pulse width gradually widens).

maychang

shaorc posted on 2018-9-15 15:04 Why do we need to set a latch to store PWM waves?

Why do we need to set a latch to store PWM waves? The main function of the latch is that once the two output terminals (pins 11 and 14) of SG3525 are low in a PWM cycle, they cannot be high again in this cycle and remain at a low level until the next PWM cycle starts.

shaorc

maychang posted on 2018-9-15 16:05 Why do we need to set a latch to store the PWM wave? The main function of the latch is to store the two output terminals (pin 11 and pin 14) of SG3525 in one P ...

If there is no latch, will the PWM go low and then go high again in one cycle? Will this cause misconduction?

maychang

shaorc posted on 2018-9-16 15:16 If there is no latch, will pwm go low and then high again in a cycle? Will this cause mis-conduction?

In the case of interference, there is a possibility of mis-conduction. Adding this latch can make the switching power supply control chip work more reliably.

maychang

shaorc posted on 2018-9-16 15:16 If there is no latch, will pwm go low and then high again in one cycle? Will this cause misconduction?

The disadvantage of adding this latch is that the output pulse (pin 11 and pin 14) cannot be very narrow. The result of my measurement is that if the output pulse is as small as 1us and then reduced (reduced duty cycle), there will be no pulse output at all. Therefore, a pulse width of 0.5us is impossible for SG3525. Some switching power supply control chips do not have this latch, such as TL494, and their output pulse width can be very small.

zhuyebb

What a rare and powerful post.

shaorc

maychang posted on 2018-9-15 15:43 Baidu's information says that it has the function of increasing the dead time. I don't understand. To understand how the dead time is formed, you need to understand how the oscillator works first...

Regarding the dead time controlled by pin 7, I saw Figure 2 in the chip manual. The oscillator output you said passes through a transistor and is output by PIN7, and then passes through an external resistor, see the 100 ohms in Figure 1, to control the charging and discharging time of the capacitor. The first question is: the oscillator output gives the gate signal to the internal transistor, and PIN7 is the collector and the emitter is grounded. If the transistor is turned on, will the electricity of the external capacitor connected to 100 ohms be discharged? The second question is: the origin of the dead time mechanism, is it to change the resistance to change the charge and discharge, that is, the speed of level change? Figure 1 Figure 2

shaorc

maychang posted on 2018-9-15 16:02 To understand the function of this latch, you must first understand the function of the part in the dotted box in the first post. This part is two four-input NOR gates. The NOR gate is any input terminal...

The high level of the chip 10-pin input will turn on an internal transistor, which discharges the external capacitor connected between the 8-pin and the ground. The high level of the 10-pin simultaneously turns off the two four-input NOR gates. The charging process of the external capacitor at the 8-pin is the soft start process of the SG3525 (the pulse width gradually widens). Two questions about soft-start [1] Figure 1 is also a screenshot from the manual. PIN10 is high, and PIN8 (Csoft-start) is soft-started directly because it is connected to ground. But when you say that the external capacitor connected between pin 8 and ground is discharged, does it mean that C1 in Figure 2 is discharged through the internal ground of the chip? [2] In Figure 2, the input of the enable signal EN, combined with the static operating point formed by R1/2/3, allows Q1 to work. If Q1 is turned on, then C1 will also discharge. If PIN10 is high, will C1 be discharged immediately? Is this the mechanism? The purpose of soft-start is to increase the duty cycle slowly to prevent it from rising too much. Figure 1 Figure 2

maychang

shaorc posted on 2018-9-17 10:59 Regarding the dead time controlled by pin 7, I saw Figure 2 in the chip manual, which is what you said. The oscillator output passes through a transistor and is output by PIN7. ...

The first question: The oscillator output gives the gate signal of the internal transistor, and PIN7 is the collector, and the emitter is grounded. If the transistor is turned on, does it discharge the electricity of the external capacitor connected to 100 ohms? That's right. It discharges the charge stored in the external timing capacitor.