Detailed explanation of ADC of TMS320F28335

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Detailed explanation of ADC of TMS320F28335 [Copy link]

The TMS320F28335 contains a 12-bit AD converter with the following features: 12-bit ADC core with built-in (sample and hold) S/H Analog input: 0.0V to 3.0V (voltages above 3.0V produce full-scale conversion results). Fast conversion rate: up to 80ns at 12.5MSPS at 25MHzADC clock 16 dedicated ADC channels. 8 channels multiplexed per sample/hold Auto-sequencing provides up to 16 "auto conversions" in a single session. Each conversion can be programmed to select any of the 16 input channels. The sequencer can operate as 2 independent 8-state sequencers, or as 1 larger 16-state sequencer (i.e. 2 cascaded 8-state sequencers). 16 result registers (separately addressable) for storing conversion values – The value of the input analog voltage is derived from: When input < 0: digital value = 0; When 03.0: digital value = 4095; Multiple triggers as sources for Start of Conversion (SOC) sequences – S/W-Software Immediate Start – ePWMM Start of Conversion – XINT2ADC Start of Conversion Flexible interrupt control allows interrupt request on each End of Sequence (EOS) or on every other EOS. The sequencer can be run in “Start/Stop” mode, allowing multiple “timing triggers” to be converted synchronously. The SOCA and SOCB triggers can be run independently in dual sequencer mode. The Sample and Hold (S/H) acquisition time window has independent prescaler control. Proper board layout is critical to achieve the specified ADC accuracy. For best possible results, the trace leading to the ADCIN pin should not be too close to the digital signal path. This is to minimize the switching noise on the digital lines due to coupling of the ADC input. Also, proper isolation techniques must be used to isolate the digital power supply from the ADC module power pins (VDD1A18, VDD2A18, VDDA2, VDDAIO). ADC not used, ADC connection It is recommended to keep the connections to the analog power pins even when the ADC is not used. Here is a summary of how the ADC pins should be connected if the ADC is not used in the application: ? VDD1A18/VDD2A18 - Connect to VDD ? VDDA2, VDDAIO - Connect to VDDIO ? VSS1AGND/VSS2AGND, VSSA2, VSSAIO - Connect to VSS ? ADCLO - Connect to VSS ? ADCREFIN - Connect to VSS ? ADCREFP/ADCREFM - Connect a 100nF capacitor to VSS ? ADCRESEXT - Connect a 20k? resistor (very loose tolerance) to VSS. ADCINAn, ADCINBn - Connect to VSS When the ADC is not in use, in order to achieve power saving, please make sure that the clock to the ADC module is not turned on. When using the ADC module in an application, the unused ADC input pins should be connected to the analog ground (VSS1AGND/VSS2AGND) ADC header file and register corresponding interpretation: struct ADCTRL1_BITS { // bits description Uint16 rsvd1:4; // 3:0 reserved Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode Cascade sequence mode Uint16 SEQ_OVRD:1; // 5 Sequencer override Sequencer generator override Uint16 CONT_RUN:1; // 6 Continuous run Continuous operation mode Uint16 CPS:1; // 7 ADC core clock pre-scalar ADC core clock pre-scalar Uint16 ACQ_PS:4; // 11:8 Acquisition window size Uint16 SUSMOD:2; // 13:12 Emulation suspend mode Uint16 RESET:1; // 14 ADC reset Uint16 rsvd2:1; // 15 reserved }; The following union is mainly used to solve the control of this register, which can be an overall assignment or a bit-by-bit assignment. union ADCTRL1_REG { Uint16 all; struct ADCTRL1_BITS bit; }; struct ADCTRL2_BITS { // bits description Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 Enhanced PWM comparator B as SEQ2 start conversion flag Uint16 rsvd1:1; // 1 reserved Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode SEQ2 terminal mode Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable SEQ2 interrupt enable Uint16 rsvd2:1; // 4 reserved Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 Start SEQ2 conversion Uint16 RST_SEQ2:1; // 6 Reset SEQ2 SEQ2 reset Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 External start of conversion for SEQ1 Uint16 EPWM_SOCA_SEQ1: 1; // 8 EPWM compare B SOC mask for SEQ1 Uint16 rsvd3:1; // 9 reserved Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable[/ size] Uint16 rsvd4:1; // 12 reserved Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable [size= 4]}; struct ADCASEQSR_BITS { // bits description Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state The state of sequence 1 Uint16 SEQ2_STATE:3 ; // 6:4 SEQ2 state Sequence 2 state Uint16 rsvd1:1; // 7 reserved Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status Sequencing counter status Uint16 rsvd2:4; // 15:12 reserved }; [ ADC maximum conversion channel number register struct ADCMAXCONV_BITS { // bits description[/ size] Uint16 MAX_CONV1:4; // 3:0 Max number of conversions Sequence 1 maximum number of conversion channels Uint16 MAX_CONV2:3; // 6:4 Max number of conversions Maximum number of conversion channels for sequence 2 Uint16 rsvd1:9; // 15:7 reserved }; ADC channel selection sort control register SEQ1 can only use ADCCHSELSEQ1 and ADCCHSELSEQ2; AEQ2 can only use ADCCHSELSEQ3 and ADCCHSELSEQ4 size] struct ADCCHSELSEQ1_BITS { // bits description Uint16 CONV00:4; // 3:0 Conversion selection 00 Uint16 CONV01:4; // 7:4 Conversion selection 01 Uint16 CONV02:4; // 11:8 Conversion selection 02 Uint16 CONV03:4; // 15:12 Conversion selection 03 }; struct ADCCHSELSEQ2_BITS { // bits description Uint16 CONV04:4; // 3:0 Conversion selection 04 Uint16 CONV05:4; // 7:4 Conversion selection 05 Uint16 CONV06:4; // 11:8 Conversion selection 06 Uint16 CONV07:4; // 15:12 Conversion selection 07 }; struct ADCCHSELSEQ3_BITS { // bits description [ size=4] Uint16 CONV08:4; // 3:0 Conversion selection 08 Uint16 CONV09:4; // 7:4 Conversion selection 09 Uint16 CONV10:4; // 11:8 Conversion selection 10 Uint16 CONV11:4; // 15:12 Conversion selection 11[/ size] }; struct ADCCHSELSEQ4_BITS { // bits description Uint16 CONV12:4; // 3:0 Conversion selection 12 Uint16 CONV13:4; // 7:4 Conversion selection 13 Uint16 CONV14:4; // 11:8 Conversion selection 14 Uint16 CONV15:4; // 15:12 Conversion selection 15 }; Control register 3 struct ADCTRL3_BITS { / / bits description Uint16 SMODE_SEL:1; // 0 Sampling mode select Sampling mode select Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider ADC Clock divider Uint16 ADCPWDN:1; // 5 ADC powerdown ADC power off? ? ? Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap /ref power down ADC reference/bandgap power down??? Uint16 rsvd1:8; // 15:8 reserved }; /size] Status Register struct ADCST_BITS { // bits description Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag Sequence 1 interrupt flag Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag Sequence 2 interrupt flag Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status Sequence 1 busy flag [/ size] Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status Sequence 2 busy flag Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear Clear sequence 1 interrupt flag Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear Clear sequence 2 interrupt flag Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 End of sequence buffer 1 Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 Uint16 rsvd1:8 ; // 15:8 reserved }; [ size=4]struct ADCREFSEL_BITS { // bits description Uint16 rsvd1:14; // 13:0 reserved Uint16 REF_SEL:2; // 15:14 Reference select Reference select? ? ? }; struct ADCOFFTRIM_BITS{ // bits description [ size=4]int16 OFFSET_TRIM:9; // 8:0 Offset Trim Offset trim? ? ? Uint16 rsvd1:7; // 15:9 reserved }; ADC register [size=4 ]struct ADC_REGS { union ADCTRL1_REG ADCTRL1; // ADC Control 1 union ADCTRL2_REG ADCTRL2; // ADC Control 2 union ADCMAXCONV_REG ADCMAXCONV; // Max conversions union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2[/size ] union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 union ADCASEQSR_REG ADCASEQSR; // Autosequence status register Uint16 ADCRESULT0; // Conversion Result Buffer 0 Uint16 ADCRESULT1; // Conversion Result Buffer 1 Uint16 ADCRESULT2; // Conversion Result Buffer 2 Uint16 ADCRESULT3; // Conversion Result Buffer 3 Uint16 ADCRESULT4; // Conversion Result Buffer 4 Uint16 ADCRESULT5; // Conversion Result Buffer 5 [size=4 ] Uint16 ADCRESULT6; // Conversion Result Buffer 6 Uint16 ADCRESULT7; // Conversion Result Buffer 7 Uint16 ADCRESULT8; // Conversion Result Buffer 8 [size =4] Uint16 ADCRESULT9; // Conversion Result Buffer 9 Uint16 ADCRESULT10; // Conversion Result Buffer 10 Uint16 ADCRESULT11; // Conversion Result Buffer 11[/ size] Uint16 ADCRESULT12; // Conversion Result Buffer 12 Uint16 ADCRESULT13; // Conversion Result Buffer 13 Uint16 ADCRESULT14; // Conversion Result Buffer 14 Uint16 ADCRESULT15; // Conversion Result Buffer 15 union ADCTRL3_REG ADCTRL3; // ADC Control 3 [size =4] union ADCST_REG ADCST; // ADC Status Register Uint16 rsvd1; Uint16 rsvd2; union ADCREFSEL_REG ADCREFSEL; / / Reference Select Register union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register }; struct ADC_RESULT_MIRROR_REGS [size =4]{ Uint16 ADCRESULT0; // Conversion Result Buffer 0 Uint16 ADCRESULT1; // Conversion Result Buffer 1 Uint16 ADCRESULT2;// Conversion Result Buffer 2 Uint16 ADCRESULT3; // Conversion Result Buffer 3 Uint16 ADCRESULT4; // Conversion Result Buffer 4 [size=4 ] Uint16 ADCRESULT5; // Conversion Result Buffer 5 Uint16 ADCRESULT6; // Conversion Result Buffer 6 Uint16 ADCRESULT7; // Conversion Result Buffer 7 Uint16 ADCRESULT8; // Conversion Result Buffer 8 Uint16 ADCRESULT9; // Conversion Result Buffer 9 Uint16 ADCRESULT10; // Conversion Result Buffer 10 Uint16 ADCRESULT11; // Conversion Result Buffer 11 Uint16 ADCRESULT12; // Conversion Result Buffer 12 Uint16 ADCRESULT13; / / Conversion Result Buffer 13 Uint16 ADCRESULT14; // Conversion Result Buffer 14 Uint16 ADCRESULT15; // Conversion Result Buffer 15 }; [size=4 ] ADC_Cal() general steps: Step one: This is the file provided by TI .def _ADC_cal ;Define the code segment name .asg "0x711C", ADCREFSEL_LOC ;ADCREFSEL_LOC is the ADC Reference Select Register, address 0x711C .sect".adc_cal" _ADC_cal MOVW DP, #ADCREFSEL_LOC >> 6 ; Now DP = 0x7100 MOV @28, #0xAAAA ; Address: 0x7100 + 28 MOV @29, #0xBBBB ;Address: 0x7100 + 29 LRETR Step 2: Add commands to ADC_Cal() FILE MEMORY {PAGE 0 :...ADC_CAL : origin = 0x380080, length = 0x000009 size] ... } SECTIONS { . .. .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD ... }[/size ] Step 3: Declare ADC_Cal() before using ADC, and enable ADC high-speed clock before using ADC_Cal(). extern void ADC_cal(void);…EALLOW; //Allow operations on protected registers ] SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; //Enable clock ADC_cal(); SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; //Turn off the clock EDIS; //Prohibit operations on protected registers ADC conversion software steps: Initialize the DSP system; Set the PIE interrupt vector table, Initialize the ADC module; Load the entry address of the ADC interrupt into the PIE interrupt vector table and enable the interrupt; Start the ADC conversion by software; Wait for the ADC interrupt; Read the ADC conversion result in the ADC interrupt, and the software starts the next ADC interrupt.

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